LPC2927FBD144,551 NXP Semiconductors, LPC2927FBD144,551 Datasheet
LPC2927FBD144,551
Specifications of LPC2927FBD144,551
935287117551
LPC2927FBD144-S
Available stocks
Related parts for LPC2927FBD144,551
LPC2927FBD144,551 Summary of contents
Page 1
LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB Rev. 5 — 28 September 2010 1. General description The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies 125 MHz, Full-speed USB 2.0 ...
Page 2
... NXP Semiconductors Other peripherals: One 10-bit ADC with 5.0 V measurement range and eight input channels with conversion times as low as 2.44 μs per channel. Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide an additional 16 analog inputs with conversion times as low as 2.44 μs per channel. ...
Page 3
... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Name LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm LPC2926FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm LPC2927FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm LPC2929FBD144 3 ...
Page 4
... NXP Semiconductors 4. Block diagram LPC2926/2927/2929 VECTORED INTERRUPT CONTROLLER CLOCK GENERATION UNIT RESET GENERATION UNIT POWER MANAGEMENT UNIT TIMER0/1 MTMR PWM0/1/2/3 3.3 V ADC1 ADC0 QUADRATURE ENCODER CAN0/1 GLOBAL ACCEPTANCE FILTER UART/LIN0/1 I2C0/1 Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA. ...
Page 5
... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description 5.2.1 General description The LPC2926/2927/2929 uses five ports: port 0 with 32 pins, ports 1 and 2 with 28 pins each, port 3 with 16 pins, and port 5 with 2 pins. Port 4 is not used. The pin to which each function is assigned is controlled by the SFSP registers in the System Control Unit (SCU) ...
Page 6
... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name Pin [1] P2[22]/SCK2/ 10 PCAP2[2]/D20 [1] P2[23]/SCS1[0]/ 11 PCAP3[0]/D21 [1] P3[6]/SCS0[3]/ 12 PMAT1[0]/TXDL1 [1] P3[7]/SCS2[1]/ 13 PMAT1[1]/RXDL1 [1] P0[30]/CAP0[2]/ 14 MAT0[2] [1] P0[31]/CAP0[3]/ 15 MAT0[3] [1] P2[24]/SCS1[1]/ 16 PCAP3[1]/D22 [1] P2[25]/SCS1[2]/ 17 PCAP3[2]/D23 V 18 SS(IO) ...
Page 7
... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name Pin [1] P1[22]/TXD0/ 35 USB_UP_LED/ CS4 [1] TMS 36 [1] TCK 37 [1] P1[21]/CAP3[3]/ 38 CAP1[3]/D7 [1] P1[20]/CAP3[2]/ 39 SCS0[1]/D6 [1] P1[19]/CAP3[1]/ 40 SCS0[2]/D5 [1] P1[18]/CAP3[0]/ 41 SDO0/D4 [1] P1[17]/CAP2[3]/ 42 SDI0/ SS(IO) [1] P1[16]/CAP2[2]/ 44 SCK0/D2 [1] P2[0]/MAT2[0]/ ...
Page 8
... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name Pin V 59 SS(CORE DD(CORE) [1] P3[13]/SDO1/ 61 EI5/IDX0 [1] P2[4]/MAT1[0]/ 62 EI0/D12 [1] P2[5]/MAT1[1]/ 63 EI1/D13 [1] P1[9]/SDO1/ 64 RXDL1/CS1 V 65 SS(IO) [1] P1[8]/SCS1[0]/ 66 TXDL1/CS0 [1] P1[7]/SCS1[3]/RXD1 [1] P1[6]/SCS1[2]/ 68 TXD1/A6 [1] P2[6]/MAT1[2]/ 69 EI2/D14 [1] P1[5]/SCS1[1]/PMAT ...
Page 9
... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name Pin [1] P1[3]/SCS2[1]/ 85 PMAT3[3]/A3 [1] P1[2]/SCS2[3]/ 86 PMAT3[2]/A2 [1] P1[1]/EI1/ 87 PMAT3[1]/ SS(CORE DD(CORE) [1] P1[0]/EI0/ 90 PMAT3[0]/A0 [1] P2[10]/ 91 PMAT0[2]/ SCS0[0] [1] P2[11]/ 92 PMAT0[3]/SCK0 [1] P0[0]/PHB0/ 93 TXDC0/D24 V 94 SS(IO) [1] P0[1]/PHA0/ 95 RXDC0/D25 [1] P0[2]/CLK_OUT/ ...
Page 10
... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name Pin V 109 DDA(ADC5V0) [3] VREFP 110 [3] VREFN 111 [4] P0[8]/IN1[0]/TXDL0/ 112 A20 [4] P0[9]/IN1[1]/ 113 RXDL0/A21 [4] P0[10]/IN1[2]/ 114 PMAT1[0]/A8 [4] P0[11]/IN1[3]/ 115 PMAT1[1]/A9 [1] P2[14]/SDA1/ 116 PCAP0[0]/BLS0 [1] P2[15]/SCL1/ ...
Page 11
... NXP Semiconductors Table 3. LQFP144 pin assignment Pin name Pin [4] P0[19]/IN2[3]/ 133 PMAT2[1]/A15 [1] P3[4]/MAT3[2]/ 134 PMAT2[4]/TXDC1 [1] P3[5]/MAT3[3]/ 135 PMAT2[5]/RXDC1 [1] P2[18]/SCS2[1]/ 136 PCAP1[1]/D16 [1] P2[19]/SCS2[0]/ 137 PCAP1[2]/D17 [4] P0[20]/IN2[4]/ 138 PMAT2[2]/A16 [4] P0[21]/IN2[5]/ ...
Page 12
... NXP Semiconductors The LPC2926/2927/2929 configures the ARM968E-S processor in little-endian byte order. All peripherals run at their own clock frequency to optimize the total system power consumption. The AHB-to-APB bridge used in the subsystems contains a write-ahead buffer one transaction deep. This implies that when the ARM968E-S issues a buffered write action to a register located on the APB side of the bridge, it continues even though the actual write may not yet have taken place ...
Page 13
... NXP Semiconductors 6.3 On-chip flash memory system The LPC2926/2927/2929 includes a 256 kB, 512 kB or 768 kB flash memory system. This memory can be used for both code and data storage. Programming of the flash memory can be accomplished via the flash memory controller or the JTAG. The flash controller also supports a 16 kB, byte-accessible on-chip EEPROM integrated on the LPC2926/2927/2929 ...
Page 14
Memory map LPC2926/2927/2929 0xFFFF FFFF VIC 0xFFFF F000 PCR/VIC reserved 0xFFFF C000 subsystem CGU1 0xFFFF B000 PMU 0xFFFF A000 RGU 0xFFFF 9000 CGU0 0xFFFF 8000 0xE00E 0000 reserved 0xE00C A000 quadrature encoder 0xE00C 9000 PWM3 0xE00C 8000 PWM2 0xE00C ...
Page 15
... NXP Semiconductors 6.6 Reset, debug, test, and power description 6.6.1 Reset and power-up behavior The LPC2926/2927/2929 contains external reset input and internal power-up reset circuits. This ensures that a reset is extended internally until the oscillators and flash have reached a stable state. See ...
Page 16
... NXP Semiconductors 6.6.3.1 ETM/ETB The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace buffer. A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured in a format that a user can easily understand. The ETB stores trace data produced by the ETM ...
Page 17
... NXP Semiconductors Two of the base clocks generated by the CGU0 are used as input into a second, dedicated CGU (CGU1). The CGU1 uses its own PLL and fractional dividers to generate two base clocks for the USB controller and one base clock for an independent clock output ...
Page 18
... NXP Semiconductors 6.7.2 Base clock and branch clock relationship Table 7 derived branch clocks. A short description is given of the hardware parts that are clocked with the individual branch clocks. In relevant cases more detailed information can be found in the specific subsystem description. Some branch clocks have special protection since they clock vital system parts of the device and should not be switched off ...
Page 19
... NXP Semiconductors Table 7. Base clock BASE_MSCSS_CLK BASE_UART_CLK BASE_ICLK0_CLK BASE_SPI_CLK BASE_TMR_CLK BASE_ADC_CLK reserved BASE_ICLK1_CLK [1] This clock is always on (cannot be switched off for system safety reasons). [2] In the peripheral subsystem parts of the timers, watchdog timer, SPI and UART have their own clock source. See [3] The clock should remain activated when system wake-up on timer or UART is required ...
Page 20
... NXP Semiconductors 6.8 Flash memory controller The flash memory has a 128-bit wide data interface and the flash controller offers two 128-bit buffer lines to improve system performance. The flash has to be programmed initially via JTAG. In-system programming must be supported by the bootloader. Flash memory contents can be protected by disabling JTAG access ...
Page 21
... NXP Semiconductors When an AHB data port read transfer requires data from a different flash word to that involved in the previous read transfer, a new flash read is done and wait states are given until the new read data is available. With dual buffering, a secondary buffer line is used, the output of the flash being considered as the primary buffer ...
Page 22
... NXP Semiconductors Table 10 Table 10. Sector number [1] 3 [1] 4 [1] 5 [1] 6 [1] 7 [1] 8 [1] 9 [1] 10 [1] Availability of sector 3 to sector 10 depends on device type, see The index sector is a special sector in which the JTAG access protection and sector security are located. The address space becomes visible by setting the FS_ISS bit and overlaps the regular flash sector’ ...
Page 23
... NXP Semiconductors Remark: If the programmed number of wait-states is more than three, flash-data reading cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative reading is active. 6.8.6 EEPROM EEPROM is a non-volatile memory mostly used for storing relatively small amounts of data, for example for storing settings. It contains one 16 kB memory block and is byte-programmable and byte-erasable ...
Page 24
... NXP Semiconductors Table 11. 32-bit system address bit field and Table 12. CS[2:0] 000 001 010 011 100 101 110 111 6.9.2 Pin description The external static-memory controller module in the LPC2926/2927/2929 has the following pins, which are combined with other functions on the port pins of the LPC2926/2927/2929 ...
Page 25
... NXP Semiconductors Fig 5. A timing diagram for writing to external memory is shown In between wait-state settings is indicated with arrows. (1) BLS has the same timing configurations that use the byte lane enable signals to connect Fig 6. LPC2926_27_29 Product data sheet CLK(SYS WSTOEN WSTOEN = 3, WST1 = 6 Reading from external memory ...
Page 26
... NXP Semiconductors Usage of the idle/turn-around time (IDCY) is demonstrated In are added between a read and a write cycle in the same external memory device. CLK(SYS) Fig 7. Address pins on the device are shared with other functions. When connecting external memories, check that the I/O pin is programmed for the correct function. Control of these settings is handled by the SCU ...
Page 27
... NXP Semiconductors 6.10.2 Clock description The GPDMA controller is clocked by CLK_SYS_DMA derived from BASE_SYS_CLK, see Section 6.11 USB interface The Universal Serial Bus (USB 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The bus supports hot plugging and dynamic configuration of the devices ...
Page 28
... NXP Semiconductors The USB OTG controller has the following features: • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). • ...
Page 29
... NXP Semiconductors 6.12 General subsystem 6.12.1 General subsystem clock description The general subsystem is clocked by CLK_SYS_GESS, see 6.12.2 Chip and feature identification The Chip/Feature ID (CFID) module contains registers which show and control the functionality of the chip. It contains identify the silicon and also registers containing information about the features enabled or disabled on the chip ...
Page 30
... NXP Semiconductors 6.12.4.1 Pin description The event router module in the LPC2926/2927/2929 is connected to the pins listed below. The pins are combined with other functions on the port pins of the LPC2926/2927/2929. Table 15 Table 15. Symbol EXTINT[0:7] CAN0 RXD CAN1 RXD I2C0_SCL I2C1_SCL LIN0 RXD LIN1 RXD ...
Page 31
... NXP Semiconductors • Debug mode with disabling of reset • Watchdog control register change-protected with key • Programmable 32-bit watchdog timer period with programmable 32-bit prescaler. 6.13.2.1 Functional description The watchdog timer consists of a 32-bit counter with a 32-bit prescaler. The watchdog should be programmed with a time-out value and then periodically restarted ...
Page 32
... NXP Semiconductors • four external outputs per timer corresponding to match registers, with the following capabilities: – Set LOW on match – Set HIGH on match – Toggle on match – Do nothing on match • Pause input pin (MSCSS timers only) The timers are designed to count cycles of the clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers ...
Page 33
... NXP Semiconductors 6.13.4 UARTs The LPC2926/2927/2929 contains two identical UARTs located at different peripheral base addresses. The key features are: • 16-byte receive and transmit FIFOs. • Register locations conform to 550 industry standard. • Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes. ...
Page 34
... NXP Semiconductors • Programmable choice of interface operation: Motorola SPI or Texas Instruments Synchronous Serial Interfaces. • Programmable data-frame size from bits. • Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts. Serial clock-rate master mode: fserial_clk ≤ f • • Serial clock-rate slave mode: fserial_clk = f • ...
Page 35
... NXP Semiconductors Table 18. Symbol SPIx SCK SPIx SDI SPIx SDO [1] Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in master mode, input in slave mode. [2] In slave mode there is only one chip select input pin, SPIx SCS0. The other chip selects have no function in slave mode ...
Page 36
... NXP Semiconductors Table 19. Symbol GPIO0 pin[31:0] GPIO1 pin[27:0] GPIO2 pin[27:0] GPIO3 pin[15:0] GPIO5 pin[19:18] 6.13.6.3 Clock description The GPIO modules are clocked by several clocks, all of which are derived from BASE_SYS_CLK; CLK_SYS_PESS and CLK_SYS_GPIOx ( 5), see Section management. The frequency of all clocks CLK_SYS_GPIOx is identical to CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK ...
Page 37
... NXP Semiconductors 6.14.1.2 Pin description The two CAN controllers in the LPC2926/2927/2929 have the pins listed below. The CAN pins are combined with other functions on the port pins of the LPC2926/2927/2929. Table 20 Table 20. Symbol CANx TXD CANx RXD 6.14.2 LIN The LPC2926/2927/2929 contain two LIN 2.0 master controllers. These can be used as dedicated LIN 2 ...
Page 38
... NXP Semiconductors receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I controlled by more than one bus master connected to it. The main features if the I • C0/1 use standard I/O pins with bit rates 400 kbit/s (Fast I not support powering off of individual devices connected to the same bus lines. • ...
Page 39
... NXP Semiconductors Figure 8 communication with the AHB system bus. Two internal timers are dedicated to this subsystem. MSCSS timer 0 can be used to generate start pulses for the ADCs and the first PWM. The second timer (MSCSS timer 1) is used to generate ‘carrier’ signals for the PWMs ...
Page 40
... NXP Semiconductors MSCSS PAUSE Fig 8. Modulation and Sampling Control SubSystem (MSCSS) block diagram LPC2926_27_29 Product data sheet AHB-TO-APB BRIDGE QEI ADC0 start synch start ADC1 MSCSS TIMER0 start synch start ADC2 PWM0 carrier synch carrier PWM1 carrier MSCSS TIMER1 carrier PWM0 TRAP ...
Page 41
... NXP Semiconductors 6.15.2 Pin description The pins of the LPC2926/2927/2929 MSCSS associated with the three ADC modules are described in Section Section Section 6.15.3 Clock description The MSCSS is clocked from a number of different sources: • CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-APB bus bridge • ...
Page 42
... NXP Semiconductors 6.15.4.1 Functional description The ADC block diagram, functionality is divided into two major parts; one part running on the MSCSS Subsystem clock, the other on the ADC clock. This split into two clock domains affects the behavior from a system-level perspective. The actual analog-to-digital conversions take place in the ADC clock domain, but system control takes place in the system clock domain ...
Page 43
... NXP Semiconductors Table 23. Symbol ADC0 IN[7:0] ADC1/2 IN[7:0] ADC2_EXT_START VREFN VREFP V DDA(ADC5V0) V DDA(ADC3V3) [1] VREFP, VREFN, V [2] The analog inputs of ADC0 are internally multiplied by a factor of 3 3.3 V, the maximum digital result is 1024 × 3 [3] V DDA(ADC5V0) Remark: The following formula only applies to ADC0: Voltage variations on VREFP (i ...
Page 44
... NXP Semiconductors 6.15.5 Pulse Width Modulator (PWM) The MSCSS in the LPC2926/2927/2929 includes four PWM modules with the following features. • Six pulse-width modulated output signals • Double edge features (rising and falling edges programmed individually) • Optional interrupt generation on match (each edge) • ...
Page 45
... NXP Semiconductors APB system bus IRQ pwm IRQ capt_match Fig 10. PWM block diagram The PWM block diagram in functionality is split into two major parts, a APB domain and a PWM domain, both of which run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects behavior from a system-level perspective ...
Page 46
... NXP Semiconductors 6.15.5.3 Master and slave mode A PWM module can provide synchronization signals to other modules (also called Master mode). The signal sync_out is a pulse of one clock cycle generated when the internal PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync_out, generated if a transfer from system registers to PWM shadow registers occurred when the PWM counter restarted ...
Page 47
... NXP Semiconductors 6.15.6.1 Pin description MSCSS timer 0 has no external pins. MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined with other functions on the port pins of the LPC2926/2927/2929. MSCSS timer 1 external pin. Table 25. Symbol MSCSS PAUSE 6.15.6.2 Clock description ...
Page 48
... NXP Semiconductors 6.15.7.1 Pin description The QEI module in the MSCSS has the following pins. These are combined with other functions on the port pins of the LPC2926/2927/2929. Table 26. Symbol QEI0 IDX QEI0 PHA QEI0 PHB 6.15.7.2 Clock description The QEI module is clocked by CLK_MSCSS_QEI, see this clock is identical to CLK_MSCSS_APB since they are derived from the same base clock BASE_MSCSS_CLK ...
Page 49
... NXP Semiconductors EXTERNAL OSCILLATOR LOW POWER RING OSCILLATOR CGU0 REGISTERS AHB2DTL BRIDGE RGU REGISTERS POR reset from watchdog counter RST (device pin) Fig 11. PCRSS block diagram 6.16.1 Clock description The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and PMU internal logic, see BASE_SYS_CLK, which can be switched off in low-power modes ...
Page 50
... NXP Semiconductors 6.16.2 Clock Generation Unit (CGU0) The key features are: • Generation of 11 base clocks, selectable from several embedded clock sources. • Crystal oscillator with power-down. • Control PLL with power-down. • Very low-power ring oscillator, always on to provide a safe clock. ...
Page 51
... NXP Semiconductors CLOCK GENERATION UNIT (CGU0) 400 kHz LP_OSC EXTERNAL PLL OSCILLATOR FREQUENCY MONITOR Fig 12. Block diagram of the CGU0 (see There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a crystal oscillator. See LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU0 itself and for BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog timer) ...
Page 52
... NXP Semiconductors Configuration of the CGU0: choice can be made from the primary and secondary clock generators according to Figure 13. Fig 13. Structure of the clock generation scheme Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be connected to either a fractional divider (FDIV[0:6 one of the outputs of the PLL or to LP_OSC/crystal oscillator directly ...
Page 53
... NXP Semiconductors generator. The RDET register keeps track of which clocks are active and inactive, and the appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock detector can also generate interrupts at clock activation and deactivation so that the system can be notified of a change in internal clock status. ...
Page 54
... NXP Semiconductors input clock CCO Fig 14. PLL block diagram Triple output phases: clock outputs can be enabled by setting register P23EN to logic 1, thus giving three clocks with a 120° phase difference. In this mode all three clocks generated by the analog section are sent to the output dividers. When the PLL has not yet achieved lock the second and third phase output dividers run unsynchronized, which means that the phase relation of the output clocks is unknown ...
Page 55
... NXP Semiconductors 6.16.3 Clock generation for USB (CGU1) The CGU1 block is functionally identical to the CGU0 block and generates two clocks for the USB interface and a dedicated output clock. The CGU1 block uses its own PLL and fractional divider. The PLLs used in CGU0 and CGU1 are identical (see The clock input to the CGU1 PLL is provided by one of two base clocks generated in the CGU0: BASE_ICLK0_CLK or BASE_ICLK1_CLK ...
Page 56
... NXP Semiconductors • Automatic reset stretching and release • Monitor function to trace resets back to source • Register write-protection mechanism to prevent unintentional resets 6.16.4.1 Functional description Each reset output is defined as a combination of reset input sources including the external reset input pins and internal power-on reset, see this table form a sort of cascade to provide the multiple levels of impact that a reset may have ...
Page 57
... NXP Semiconductors 6.16.4.2 Pin description The RGU module in the LPC2926/2927/2929 has the following pins. RGU pins. Table 31. Symbol RST 6.16.5 Power Management Unit (PMU) This module enables software to actively control the system’s power consumption by disabling clocks not required in a particular operating mode. ...
Page 58
... NXP Semiconductors Table 32. Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’ Indicates that the related register bit is readable and writable ...
Page 59
... NXP Semiconductors Table 32. Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’ Indicates that the related register bit is readable and writable ...
Page 60
... NXP Semiconductors 6.17.1 Functional description The Vectored Interrupt Controller routes incoming interrupt requests to the ARM processor. The interrupt target is configured for each interrupt request input of the VIC. The targets are defined as follows: • Target 0 is ARM processor FIQ (fast interrupt service). ...
Page 61
... NXP Semiconductors 7. Limiting values Table 33. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Supply pins P total power dissipation tot V core supply voltage DD(CORE) V oscillator and PLL supply DD(OSC_PLL) voltage V 3.3 V ADC analog supply DDA(ADC3V3) voltage V 5.0 V ADC analog supply ...
Page 62
... NXP Semiconductors Table 33. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter ESD V electrostatic discharge ESD voltage [1] Based on package heat transfer, not device power consumption. [2] Peak current must be limited at 25 times average current. [3] For I/O Port 0, the maximum input voltage is defined by V ...
Page 63
... NXP Semiconductors 8. Static characteristics Table 34. Static characteristics DD(CORE) DD(OSC_PLL) DD(IO) − ° ° +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise vj [1] specified. Symbol Parameter Supplies Core supply V core supply voltage DD(CORE) I core supply current ...
Page 64
... NXP Semiconductors Table 34. Static characteristics DD(CORE) DD(OSC_PLL) DD(IO) − ° ° +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise vj [1] specified. Symbol Parameter V LOW-level input voltage IL V hysteresis voltage hys I HIGH-level input leakage LIH ...
Page 65
... NXP Semiconductors Table 34. Static characteristics DD(CORE) DD(OSC_PLL) DD(IO) − ° ° +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise vj [1] specified. Symbol Parameter I LOW-level output current OL I HIGH-level short-circuit OHS output current I LOW-level short-circuit ...
Page 66
... NXP Semiconductors Table 35. ADC static characteristics DDA(ADC3V3) amb Symbol Parameter V voltage on pin VREFN VREFN V voltage on pin VREFP VREFP V analog input voltage IA Z input impedance i C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error ...
Page 67
... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 17. ADC characteristics LPC2926_27_29 Product data sheet ...
Page 68
... NXP Semiconductors 8.1 Power consumption I DD(CORE) (mA) Fig 18 DD(CORE) (mA) Fig 19. I LPC2926_27_29 Product data sheet °C; active mode entered executing code from flash; core voltage 1.8 V; all Conditions: T amb peripherals enabled but not configured to run. at different core frequencies (active mode) DD(CORE) 80 125 MHz ...
Page 69
... NXP Semiconductors I DD(CORE) (mA) Fig 20. 8.2 Electrical pin characteristics V (mV) Fig 21. Typical LOW-level output voltage versus LOW-level output current LPC2926_27_29 Product data sheet 80 125 MHz 60 100 MHz 80 MHz 40 40 MHz 20 10 MHz 0 −40 −15 10 Conditions: active mode entered executing code from flash; core voltage 1.8 V; all peripherals enabled but not configured to run ...
Page 70
... NXP Semiconductors V Fig 22. Typical HIGH-level output voltage versus HIGH-level output current I (μA) Fig 23. Typical pull-down current versus temperature LPC2926_27_29 Product data sheet 3.5 OH (V) 3.0 2.5 2.0 1.0 2 3.3 V. DD(IO) 80 I(pd −40 − 3 All information provided in this document is subject to legal disclaimers. ...
Page 71
... NXP Semiconductors I (μA) Fig 24. Typical pull-up current versus temperature LPC2926_27_29 Product data sheet −20 I(pu) −40 −60 −80 −100 −40 − All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB ...
Page 72
... NXP Semiconductors 9. Dynamic characteristics 9.1 Dynamic characteristics: I/O and CLK_OUT pins, internal clock, oscillators, PLL, and CAN Table 36. Dynamic characteristics DD(CORE) DD(OSC_PLL) DD(IO) ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter I/O pins t HIGH to LOW transition THL time ...
Page 73
... NXP Semiconductors f ref(RO) (kHz) Fig 25. Low-power ring oscillator thermal characteristics LPC2926_27_29 Product data sheet 520 510 500 490 480 −40 −15 10 All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 September 2010 LPC2926/2927/2929 ARM9 microcontroller with CAN, LIN, and USB 1 ...
Page 74
... NXP Semiconductors 9.2 USB interface Table 37. Dynamic characteristics: USB pins (full-speed) Ω pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...
Page 75
... NXP Semiconductors 9.3 Dynamic characteristics: I Table 38. Dynamic characteristic DD(CORE) DD(OSC_PLL) DD(IO) ground; positive currents flow into the IC; unless otherwise specified Symbol Parameter t output fall time f(o) [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T temperature on wafer level. Cased products are tested at T test conditions to cover the specified temperature and power supply voltage range. Typical ratings are not guaranteed. The values listed are at room temperature (25 ° ...
Page 76
... NXP Semiconductors 9.4 Dynamic characteristics: SPI Table 39. Dynamic characteristics of SPI pins DD(CORE) DD(OSC_PLL) DD(IO) − ° ° +85 C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise vj [1] specified. Symbol Parameter f SPI operating frequency SPI t SPI_MISO set-up time ...
Page 77
... NXP Semiconductors 9.5 Dynamic characteristics: flash memory and EEPROM Table 40. − amb V DDA(ADC3V3) Symbol N endu t ret t prog init t wr(pg) t fl(BIST) t a(clk) t a(A) [1] Number of program/erase cycles. Table 41. − amb V DDA(ADC3V3) Symbol f clk N endu t ret LPC2926_27_29 Product data sheet Flash characteristics ° ° ...
Page 78
... NXP Semiconductors 9.6 Dynamic characteristics: external static memory Table 42. External static memory interface dynamic characteristics DD(CORE) DD(OSC_PLL) DD(IO) [1] ground. Symbol Parameter T clock cycle time CLCL t internal read access time a(R)int t internal write access time a(W)int Read cycle parameters t CS LOW to address valid ...
Page 79
... NXP Semiconductors CSLOEL OE/BLS Fig 28. External memory read access CS BLS Fig 29. External memory write access LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB t CSLAV t su(DQ OELAV BLSLAV OELOEH BLSLBLSH t CSLDV t BLSLBLSH t CSLBLSL t CSLWEL t WELDV t CSLDV All information provided in this document is subject to legal disclaimers. ...
Page 80
... NXP Semiconductors 9.7 Dynamic characteristics: ADC Table 43. ADC dynamic characteristics DD(CORE) DD(OSC_PLL) DD(IO) [1] ground. Symbol Parameter 5.0 V ADC0 f ADC input frequency i(ADC) f maximum sampling rate s(max) t conversion time conv 3.3 V ADC1/2 f ADC input frequency i(ADC) f maximum sampling rate s(max) t conversion time ...
Page 81
... NXP Semiconductors core frequency (MHz) Fig 30. Core operating frequency versus temperature for different core voltages. core frequency (MHz) Fig 31. Core operating frequency versus core voltage for different temperatures LPC2926_27_29 Product data sheet 145 V = 1.95 V DD(CORE) 135 V = 1.8 V DD(CORE) 125 V = 1.65 V DD(CORE) ...
Page 82
... NXP Semiconductors 10.2 Suggested USB interface solutions LPC29xx Fig 32. LPC2926/2927/2929 USB interface on a self-powered device LPC29xx Fig 33. LPC2926/2927/2929 USB interface on a bus-powered device LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 kΩ ...
Page 83
... NXP Semiconductors USB_RST LPC29xx USB_SCL USB_SDA USB_INT USB_D+ USB_D− Fig 34. LPC2926/2927/2929 USB OTG port configuration USB_UP_LED USB_CONNECT LPC29xx USB_D+ USB_D− USB_VBUS Fig 35. LPC2926/2927/2929 USB device port configuration LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO) ...
Page 84
... NXP Semiconductors 10.3 SPI signal forms SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 36. SPI timing in master mode SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 37. SPI timing in slave mode LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB SDOn MSB OUT ...
Page 85
... NXP Semiconductors 10.4 XIN_OSC input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional i capacitor to ground C mode, a minimum of 200 mV (RMS) is needed ...
Page 86
... NXP Semiconductors 11. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
Page 87
... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
Page 88
... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
Page 89
... NXP Semiconductors Fig 40. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. LPC2926_27_29 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...
Page 90
... NXP Semiconductors 13. Abbreviations Table 46. Abbreviation AHB AMBA APB BIST CCO CISC DMA DSP DTL EOP ETB ETM FIQ GPDMA IRQ LIN LSB MAC MSB MSC PHY PLL Q-SPI RISC SFSP TAP TTL UART 14. References [1] UM10316 — LPC29xx user manual [2] ARM — ARM web site [3] ARM-SSP — ...
Page 91
... NXP Semiconductors 15. Revision history Table 47. Revision history Document ID Release date LPC2926_27_29 v.5 20100928 Modifications: LPC2927_29 v.4 20100414 Modifications: LPC2927_29 v.3 20091208 LPC2927_29 v.2 20090622 LPC2927_29 v.1 20090115 LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Data sheet status Product data sheet • ...
Page 92
... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
Page 93
... LPC2926_27_29 Product data sheet ARM9 microcontroller with CAN, LIN, and USB own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
Page 94
... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2.1 General description . . . . . . . . . . . . . . . . . . . . . 5 5.2.2 LQFP144 pin assignment . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . 11 6.1 Architectural overview . . . . . . . . . . . . . . . . . . 11 6.2 ARM968E-S processor . . . . . . . . . . . . . . . . . . 12 6 ...
Page 95
... NXP Semiconductors 6.15.6.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 47 6.15.7 Quadrature Encoder Interface (QEI 6.15.7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 48 6.15.7.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 48 6.16 Power, Clock and Reset Control Subsystem (PCRSS 6.16.1 Clock description . . . . . . . . . . . . . . . . . . . . . . 49 6.16.2 Clock Generation Unit (CGU0 6.16.2.1 Functional description 6.16.2.2 PLL functional description . . . . . . . . . . . . . . . 53 6.16.2.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 54 6 ...