LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 48

IC ARM CORTEX MCU 512K 100-LQFP

LPC1767FBD100,551

Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr

Specifications of LPC1767FBD100,551

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-4967
935289808551

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC1767FBD100,551
Quantity:
9 999
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 10.
T
[1]
[2]
[3]
Table 11.
T
[1]
LPC1768_67_66_65_64_3
Product data sheet
Symbol
f
t
t
Symbol
common to input and output
t
t
t
t
output
t
input
t
t
SCL
f
SU;DAT
r
f
WH
WL
v(Q)
su(D)
h(D)
amb
amb
Parameters are valid over operating temperature range unless otherwise specified.
Bus capacitance C
CCLK = 20 MHz; peripheral clock to the I
signal in the I
CCLK = PCLK = 20 MHz; I
=
=
40
40
°
°
Dynamic characteristics: I
Dynamic characteristic: I
Parameter
rise time
fall time
pulse width HIGH
pulse width LOW
data output valid time
data input set-up time
data input hold time
C to +85
C to +85
2
11.4 I
11.5 I
S-bus specification.
Parameter
SCL clock frequency
fall time
data set-up time
b
°
°
in pF (50 pF), external pull-up resistance = 218 Ω.
C; V
C.
2
2
Fig 12. I
DD(3V3)
C-bus
S-bus interface (LPC1768/67/66/65 only)
2
C-bus interface configured in master mode.
over specified ranges.
2
C-bus pins clock timing
2
C-bus pins (Fast-mode Plus)
2
Conditions
on pins I2STX_CLK and
I2SRX_CLK
on pins I2STX_CLK and
I2SRX_CLK
on pin I2STX_SDA;
on pin I2STX_WS
on pin I2SRX_SDA
on pin I2SRX_SDA
2
SDA
SCL
S-bus interface pins
S-bus interface PCLK =
P
Rev. 03 — 19 November 2009
[1][2][3]
Conditions
-
S
CCLK
4
; I
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
2
S clock cycle time T
Min
-
-
0.495 × T
-
-
-
3.5
4.0
LPC1768/67/66/65/64
Min
-
-
50
32-bit ARM Cortex-M3 microcontroller
cy(clk)
cy(clk)
Typ
-
-
-
-
-
-
-
-
= 1600 ns, corresponds to the SCK
Typ
-
-
-
t
f
t
Max
35
35
-
0.505 × T
30
30
-
-
SU;DAT
002aae860
© NXP B.V. 2009. All rights reserved.
Max
1
45
-
cy(clk)
Unit
ns
ns
-
ns
ns
ns
ns
ns
Unit
MHz
ns
ns
48 of 65

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