LPC2388FBD144,551 NXP Semiconductors, LPC2388FBD144,551 Datasheet
LPC2388FBD144,551
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LPC2388 Single-chip 16-bit/32-bit micro; 512 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC Rev. 2 — 13 July 2010 1. General description The LPC2388 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that ...
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... NXP Semiconductors General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP serial interfaces, the I card port, as well as for memory-to-memory transfers. Serial Interfaces: Ethernet MAC with associated DMA controller. These functions reside on an independent AHB. ...
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... NXP Semiconductors 4 MHz internal RC oscillator trimmed accuracy that can optionally be used as the system clock. When used as the CPU clock, does not allow CAN and USB to run. On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal ...
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... NXP Semiconductors 5. Block diagram LPC2388 P0, P1, P2, P3, P4 HIGH-SPEED GPI/O 104 PINS TOTAL ETHERNET RMII(8) MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2, TIMER2/TIMER3 2 × MAT0/MAT1/ MAT3 6 × PWM1 2 × PCAP1 LEGACY GPI/O P0 PINS TOTAL 8 × AD0 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. LPC2388 pinning 6.2 Pin description Table 3. Pin description Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/RD1/TXD/ 66 I/O SDA1 I O I/O [1] P0[1]/TD1/RXD3/ 67 I/O SCL1 O I I/O [1] P0[2]/TXD0 141 I/O O [1] P0[3]/RXD0 142 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[5]/ 115 I/O I2SRX_WS/ I/O TD2/CAP2[ [1] P0[6]/ 113 I/O I2SRX_SDA/ I/O SSEL1/MAT2[0] I/O O [1] P0[7]/ 112 I/O I2STX_CLK/ I/O SCK1/MAT2[1] I/O O [1] P0[8]/ 111 I/O I2STX_WS/ I/O MISO1/MAT2[2] I/O O [1] P0[9]/ 109 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[14]/ 48 I/O USB_HSTEN2/ O USB_CONNECT2/ O SSEL1 I/O [1] P0[15]/TXD1/ 89 I/O SCK0/SCK O I/O I/O [1] P0[16]/RXD1/ 90 I/O SSEL0/SSEL I I/O I/O [1] P0[17]/CTS1/ 87 I/O MISO0/MISO I I/O I/O [1] P0[18]/DCD1/ 86 I/O MOSI0/MOSI I I/O I/O [1] P0[19]/DSR1/ ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [2] P0[23]/AD0[0]/ 13 I/O I2SRX_CLK/ I CAP3[0] I/O I [3] P0[24]/AD0[1]/ 11 I/O I2SRX_WS/ I CAP3[1] I/O I [2] P0[25]/AD0[2]/ 10 I/O I2SRX_SDA/ I TXD3 I/O O [2] P0[26]/AD0[3]/ 8 I/O AOUT/RXD3 [4] P0[27]/SDA0 35 I/O I/O [4] P0[28]/SCL0 34 I/O ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P1[10]/ 129 I/O ENET_RXD1 I [1] P1[14]/ 128 I/O ENET_RX_ER I [1] P1[15]/ 126 I/O ENET_REF_CLK I [1] P1[16]/ 125 I/O ENET_MDC O [1] P1[17]/ 123 I/O ENET_MDIO I/O [1] P1[18]/ 46 I/O USB_UP_LED1/ O PWM1[1]/ CAP1[ [1] P1[19]/ 47 I/O ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P1[25]/ 56 I/O USB_LS1/ O USB_HSTEN1/ O MAT1[1] O [1] P1[26]/ 57 I/O USB_SSPND1/ O PWM1[6]/ O CAP0[0] I [1] P1[27]/ 61 I/O USB_INT1/ I USB_OVRCR1/ I CAP0[1] I [1] P1[28]/ 63 I/O USB_SCL1/ I/O PCAP1[0]/ I MAT0[0] O [1] P1[29]/ 64 I/O USB_SDA1/ I/O PCAP1[1]/ I MAT0[1] O [2] ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P2[2]/PWM1[3]/ 105 I/O CTS1/ O PIPESTAT1 I O [1] P2[3]/PWM1[4]/ 100 I/O DCD1/ O PIPESTAT2 I O [1] P2[4]/PWM1[5]/ 99 I/O DSR1/ O TRACESYNC I O [1] P2[5]/PWM1[6]/ 97 I/O DTR1/ O TRACEPKT0 O O [1] P2[6]/PCAP1[0]/ 96 I/O RI1/ I TRACEPKT1 I O [1] ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [6] P2[11]/EINT1/ 75 I/O MCIDAT1/ I I2STX_CLK O I/O [6] P2[12]/EINT2/ 73 I/O MCIDAT2/ I I2STX_WS O I/O [6] P2[13]/EINT3/ 71 I/O MCIDAT3/ I I2STX_SDA O I/O P3[0] to P3[31] I/O [1] P3[0]/D0 137 I/O I/O [1] P3[1]/D1 140 I/O I/O [1] P3[2]/D2 144 I/O ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P3[25]/MAT0[0]/ 39 I/O PWM1[ [1] P3[26]/MAT0[1]/ 38 I/O PWM1[ P4[0] to P4[31] I/O [1] P4[0]/A0 52 I/O I/O [1] P4[1]/A1 55 I/O I/O [1] P4[2]/A2 58 I/O I/O [1] P4[3]/A3 68 I/O I/O [1] P4[4]/A4 72 I/O I/O [1] P4[5]/A5 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P4[24]/OE 127 I/O O [1] P4[25]/BLS0 124 I/O O [1] P4[28]/MAT2[0]/ 118 I/O TXD3 O O [1] P4[29]/MAT2[1]/ 122 I/O RXD3 O I [1] P4[30]/CS0 130 I/O O [1] P4[31]/CS1 134 I/O O [8] ALARM ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type V 41, 62, I DD(3V3) 77, 102, 114, [13] 138 n.c. 21, 81, I [14 18, 60, I DD(DCDC)(3V3) [15] 121 [16 DDA [16] VREF 17 I [16] VBAT tolerant pad providing digital I/O functions with TTL levels and hysteresis. [ tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input, digital section of the pad is disabled ...
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... NXP Semiconductors 7. Functional description 7.1 Architectural overview The LPC2388 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external memory, and the AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order ...
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... NXP Semiconductors The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. ...
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... NXP Semiconductors 3.75 GB Fig 3. 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... NXP Semiconductors FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device ...
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... NXP Semiconductors • Static memory features include: – Asynchronous page mode read – Programmable Wait States (WST) – Bus turnaround delay – Output enable and write enable delays – Extended wait 7.8 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2388 peripherals to have DMA support ...
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... NXP Semiconductors • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Interrupt masking. The DMA error and DMA terminal count interrupt requests can be masked. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking ...
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... NXP Semiconductors via the EMC, as well as the SRAM located on another AHB not being used by the USB block. However, using memory other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet access to memory and increase the loading of its AHB. The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus ...
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... NXP Semiconductors The LPC2388 USB interface includes a device, host, and OTG controller. Details on typical USB interfacing solutions can be found in 7.11.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller ...
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... NXP Semiconductors 7.11.3.1 Features • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev ...
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... NXP Semiconductors 10-bit conversion time 2.44 s • • Burst conversion mode for single or multiple inputs • Optional conversion on transition of input pin or Timer Match signal • Individual result registers for each ADC channel to reduce interrupt overhead 7.14 10-bit DAC The DAC allows the LPC2388 to generate a variable analog output. The maximum output value of the DAC ...
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... NXP Semiconductors 7.16.1 Features • Compliant with SPI specification • Synchronous, Serial, Full Duplex Communication • Combined SPI master and slave • Maximum data bit rate of one eighth of the input clock rate • 8 bits to 16 bits per transfer 7.17 SSP serial I/O controller The LPC2388 contains two SSP controllers ...
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... NXP Semiconductors 2 The I C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line (SCL), and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed ...
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... NXP Semiconductors • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I 7.21 General purpose 32-bit timers/external event counters The LPC2388 includes four 32-bit Timer/Counters ...
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... NXP Semiconductors controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. ...
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... NXP Semiconductors • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (T multiples of T • ...
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... NXP Semiconductors 7.25 Clocking and power control 7.25.1 Crystal oscillators The LPC2388 includes three independent oscillators. These are the Main Oscillator, the Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the PLL and ultimately the CPU ...
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... NXP Semiconductors The PLL is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL is enabled by software only. The program must configure and activate the PLL, wait for the PLL to lock, then connect to the PLL as a clock source. 7.25.3 Wake-up timer The LPC2388 begins operation at power-up and when awakened from Power-down and Deep power-down modes by using the 4 MHz IRC oscillator as the clock source ...
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... NXP Semiconductors 7.25.4.2 Sleep mode In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later ...
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... NXP Semiconductors 7.25.4.5 Power domains The LPC2388 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the battery RAM. On the LPC2388, I/O pads are powered by the 3 DD(DCDC)(3V3) the CPU and most of the peripherals. ...
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... NXP Semiconductors The second stage of low-voltage detection asserts Reset to inactivate the LPC2388 when the voltage on the V the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below which point the power-on reset circuitry maintains the overall Reset. ...
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... NXP Semiconductors 7.26.5 External interrupt inputs The LPC2388 includes edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 7.26.6 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000 ...
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... NXP Semiconductors addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed ...
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... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter supply voltage DD(DCDC)(3V3) (3 analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF ...
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... NXP Semiconductors 9. Thermal characteristics The average chip junction temperature, T equation amb • T amb • R th(j-a) • The internal power dissipation is the product of I the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 5. Thermal characteristics ...
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... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage (3 analog 3.3 V pad DDA supply voltage V input voltage on pin i(VBAT) VBAT ...
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... NXP Semiconductors Table 6. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I I/O latch-up current latch V input voltage I V output voltage O V HIGH-level input IH voltage V LOW-level input IL voltage V hysteresis voltage hys V HIGH-level output OH voltage V LOW-level output ...
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... NXP Semiconductors Table 6. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V output voltage on pin o(RTCX2) RTCX2 USB pins I OFF-state output OZ current V bus supply voltage BUS V differential input DI sensitivity voltage V differential common CM mode voltage range ...
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... NXP Semiconductors 10.1 Power-down mode I DD(IO) (μA) Fig 4. I (μA) Fig 5. LPC2388 Product data sheet −2 −4 −40 − 3 i(VBAT) DD(DCDC)(3V3) amb I/O maximum supply current I 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) RTC battery maximum supply current I mode All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors I DD(DCDC)pd(3v3) Fig 6. 10.2 Deep power-down mode I DD(IO) (μA) Fig 7. LPC2388 Product data sheet 800 (μA) 600 400 V = 3.3 V DD(DCDC)(3V3) 200 V = 3.0 V DD(DCDC)(3V3) 0 −40 − 3 DD(3V3) i(VBAT) amb Total DC-to-DC converter supply current I in Power-down mode 300 ...
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... NXP Semiconductors I (μA) Fig 8. I DD(DCDC)dpd(3v3) Fig 9. LPC2388 Product data sheet 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) RTC battery maximum supply current I power-down mode 100 (μ 3.3 V DD(DCDC)(3V3 3.0 V DD(DCDC)(3V3 −40 − 3 DD(3V3) i(VBAT) ...
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... NXP Semiconductors 10.3 Electrical pin characteristics V Fig 10. Typical HIGH-level output voltage V (mA) Fig 11. Typical LOW-level output current I LPC2388 Product data sheet 3 °C 25 °C 3.2 −40 °C 2.8 2.4 2 Conditions 3.3 V; standard port pins. DD(3V3 0.2 Conditions 3.3 V; standard port pins. ...
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... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics +85 C for commercial applications; V amb Symbol Parameter External clock (see Figure 12) f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time CLCH ...
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... NXP Semiconductors 11.1 Internal oscillators Table 8. Dynamic characteristic: internal oscillators +85 C; 3.0 V amb Symbol Parameter f internal RC oscillator frequency osc(RC) f RTC input frequency i(RTC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. ...
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... NXP Semiconductors 11.4 Flash memory Table 11. Dynamic characteristics of flash +85 C, unless otherwise specified; V amb ground. Symbol Parameter N endurance endu t retention time ret [1] Number of program/erase cycles. [2] t specified for < 1 ppm. ret LPC2388 Product data sheet = 3 3.6 V; all voltages are measured with respect to ...
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Static external memory interface Table 12. Dynamic characteristics: Static external memory interface pF amb DD(DCDC)(3V3) Symbol Parameter Conditions [1] Common to read and write ...
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... NXP Semiconductors 11.6 Timing CS addr data t CSLOEL OE Fig 13. External memory read access CS BLS addr data OE Fig 14. External memory write access LPC2388 Product data sheet t CSLAV OELAV t OELOEH t CSLAV t BLSLBLSH t t CSLBLSL BLSDV t CSLDV All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors T PERIOD differential data lines Fig 15. Differential data-to-EOP transition skew and EOP width shifting edges SCK MOSI MISO Fig 16. MISO line set-up time in SSP Master mode LPC2388 Product data sheet crossover point crossover point differential data to SE0/EOP skew n × PERIOD ...
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... NXP Semiconductors 12. ADC electrical characteristics Table 13. ADC electrical characteristics 2 3 DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error T R voltage source interface ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 17. ADC characteristics LPC2388 Product data sheet ...
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... NXP Semiconductors AD0[y] Fig 18. Suggested ADC interface - LPC2388 AD0[y] pin LPC2388 Product data sheet LPC23XX 20 kΩ SAMPLE All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 July 2010 LPC2388 Single-chip 16-bit/32-bit microcontroller R vsi AD0[y] V EXT 002aac610 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 13. DAC electrical characteristics Table 14. DAC electrical characteristics 3 3 DDA amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G C load capacitance L R load resistance L 14. Application information 14.1 Suggested USB interface solutions LPC23XX Fig 19 ...
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... NXP Semiconductors LPC23XX Fig 20. LPC2388 USB interface on a bus-powered device (applies to USB ports 1 and 2) LPC2388 Product data sheet V DD(3V3 USB_UP_LED 1.5 kΩ V BUS Ω USB_D Ω USB_D− All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 July 2010 LPC2388 ...
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... NXP Semiconductors RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC2388 USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 21. LPC2388 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2388 Product data sheet RESET_N ADR/PSW OE_N/INT_N V DD SPEED ...
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... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC2388 USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 22. LPC2388 USB OTG port configuration: VP_VM mode LPC2388 Product data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1301 ADR/PSW SPEED SUSPEND SCL SDA INT_N V DD All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC2388 USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 V BUS Fig 23. LPC2388 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2388 Product data sheet Ω 33 Ω 15 kΩ 15 kΩ ENA 5 V LM3526-L ...
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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC2388 USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 24. LPC2388 USB OTG port configuration: USB port 1 host, USB port 2 host 14.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a ...
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... NXP Semiconductors In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in ...
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... NXP Semiconductors Table 16. Fundamental oscillation frequency F 15 MHz to 20 MHz 20 MHz to 25 MHz 14.3 RTC 32 kHz oscillator component selection Fig 27. RTC oscillator modes and models: oscillation mode of operation and external The RTC external oscillator circuit is shown in integrated on chip, only a crystal, the capacitances C externally to the microcontroller ...
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... NXP Semiconductors 14.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain ...
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... NXP Semiconductors 14.6 Reset pin configuration Fig 29. Reset pin configuration LPC2388 Product data sheet reset GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 July 2010 LPC2388 Single-chip 16-bit/32-bit microcontroller ESD ESD V SS 002aaf274 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 15. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Abbreviations Table 18. Acronym ADC AHB AMBA APB BLS BOD CAN CTS DAC DCC DMA DSP EOP ETM GPIO IrDA JTAG MII OTG PHY PLL PWM RMII RTS SE0 SPI SSI SSP TTL UART USB LPC2388 Product data sheet Acronym list ...
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... NXP Semiconductors 17. Revision history Table 19. Revision history Document ID Release date LPC2388 v.2 20100713 • Modifications: Table 3 “Pin • Table 3 “Pin • Table 4 “Limiting • Table 6 “Static • Table 6 “Static • Table 6 “Static • Table 6 “Static • Table 6 “Static I • Added • ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... For sales office addresses, please send an email to: LPC2388 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . 16 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 16 7.2 On-chip flash programming memory . . . . . . . 17 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 17 7 ...
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... NXP Semiconductors 11.5 Static external memory interface . . . . . . . . . . 50 11.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12 ADC electrical characteristics . . . . . . . . . . . . 53 13 DAC electrical characteristics . . . . . . . . . . . . 56 14 Application information 14.1 Suggested USB interface solutions . . . . . . . . 56 14.2 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.3 RTC 32 kHz oscillator component selection . . 63 14.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines ...