lpc2388 NXP Semiconductors, lpc2388 Datasheet
lpc2388
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lpc2388 Summary of contents
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... Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. The LPC2388 is ideal for multi-purpose serial communication applications. It incorporates a 10/100 Ethernet Media Access Controller (MAC), USB device/host/OTG with ...
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... On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz. LPC2388_0 Preliminary data sheet 2 S port, and the Secure Digital/MultiMediaCard (SD/MMC) card 2 C-bus interfaces (one with open-drain and two with standard port pins). Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... Description LPC2388FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 1.4 mm 4.1 Ordering options Table 2. Ordering options Type number Flash SRAM (kB) (kB) LPC2388FBD144 512 LPC2388_0 Preliminary data sheet External bus Ether USB net device host OTG ...
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... AD0 A/D CONVERTER AOUT D/A CONVERTER VBAT 2 kB BATTERY RAM power domain 2 power domain 2 RTCX1 RTC RTCX2 OSCILLATOR WATCHDOG TIMER SYSTEM CONTROL Fig 1. LPC2388 block diagram LPC2388_0 Preliminary data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 512 kB PLL TEST/DEBUG FLASH INTERFACE ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. LPC2388 pinning 6.2 Pin description Table 3. Pin description Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/RD1/TXD/ 66 I/O SDA1 I O I/O [1] P0[1]/TD1/RXD3/ 67 I/O SCL1 O I I/O [1] P0[2]/TXD0 141 I/O O [1] P0[3]/RXD0 142 I/O I [1] P0[4]/ 116 I/O I2SRX_CLK/ I/O RD2/CAP2[ LPC2388_0 Preliminary data sheet 1 108 LPC2388FBD144 36 73 002aad333 Description Port 0: Port 32-bit I/O port with individual direction controls for each bit ...
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... USB_UP_LED2 — USB port 2 Good Link LED indicator LOW when device is configured (non-control endpoints enabled HIGH when the device is not configured or during global suspend. MOSI1 — Master Out Slave In for SSP1. AD0[7] — A/D converter 0, input 7. Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip 2 S-bus specification. 2 S-bus specification. ...
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... RD1 — CAN1 receiver input. P0[22] — General purpose digital input/output pin. RTS1 — Request to Send output for UART1. MCIDAT0 — Data line for SD/MMC interface. TD1 — CAN1 transmitter output. Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... P1[4] — General purpose digital input/output pin. ENET_TX_EN — Ethernet transmit data enable. P1[8] — General purpose digital input/output pin. ENET_CRS — Ethernet carrier sense. P1[9] — General purpose digital input/output pin. ENET_RXD0 — Ethernet receive data. Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip 2 S-bus specification. 2 S-bus specification. 2 S-bus specification ...
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... P1[24] — General purpose digital input/output pin. USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver). PWM1[5] — Pulse Width Modulator 1, channel 5 output. MOSI0 — Master Out Slave in for SSP0. Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... TRACECLK — Trace Clock. P2[1] — General purpose digital input/output pin. PWM1[2] — Pulse Width Modulator 1, channel 2 output. RXD1 — Receiver input for UART1. PIPESTAT0 — Pipeline Status, bit 0. Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... P2[10] — General purpose digital input/output pin. Note: LOW on this pin while RESET is LOW forces on-chip boot-loader to take over control of the part after a reset. EINT0 — External interrupt 0 input. Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... CAP0[0] — Capture input for Timer 0, channel 0. PCAP1[0] — Capture input for PWM1, channel 0. P3[24] — General purpose digital input/output pin. CAP0[1] — Capture input for Timer 0, channel 1. PWM1[1] — Pulse Width Modulator 1, output 1. Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip 2 S-bus specification. 2 S-bus specification. ...
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... A13 — External memory address line 13. P4[14] — General purpose digital input/output pin. A14 — External memory address line 14. P4[15] — General purpose digital input/output pin. A15 — External memory address line 15. Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2388 being in Reset state. external reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0 ...
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... Pad provides special analog functionality. 7. Functional description 7.1 Architectural overview The LPC2388 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external memory, and the AMBA APB for connection to other on-chip peripheral functions ...
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... NXP Semiconductors The LPC2388 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC. The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM ...
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... The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at SRAM speeds of 72 MHz. The LPC2388 provides a minimum of 100 000 write/erase cycles and 20 years of data retention. 7.3 On-chip SRAM The LPC2388 includes a SRAM memory reserved for the ARM processor exclusive use ...
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... GB 2.0 GB 1.0 GB 0.0 GB Fig 3. LPC2388 memory map 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... External memory controller The LPC2388 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals ...
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... Output enable and write enable delays – Extended wait 7.8 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2388 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination ...
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... The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2388 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory ...
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... Physical interface: – Attachment of external PHY chip through standard RMII interface. – PHY register access is available via the MIIM interface. LPC2388_0 Preliminary data sheet Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... Supports SoftConnect and GoodLink features. • While the USB is in the Suspend mode, the LPC2388 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with the DMA RAM all non-control endpoints. ...
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... Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • Full CAN messages can generate interrupts. LPC2388_0 Preliminary data sheet Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip 2 C interface © NXP B.V. 2008. All rights reserved ...
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... Optional conversion on transition of input pin or Timer Match signal • Individual result registers for each ADC channel to reduce interrupt overhead 7.14 10-bit DAC The DAC allows the LPC2388 to generate a variable analog output. The maximum output value of the DAC is V 7.14.1 Features • 10-bit DAC • ...
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... UART3 includes an IrDA mode to support infrared communication. 7.16 SPI serial I/O controller The LPC2388 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master ...
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... The I be controlled by more than one bus master connected to it. 2 The I C-bus implemented in LPC2388 supports bit rates up to 400 kbit/s (Fast I 7.19.1 Features • standard I • ...
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... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2388. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...
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... Features • LPC2388 has one PWM block with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow single edge controlled or 3 double edge controlled PWM outputs mix of both types. The match registers also allow: – ...
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... RTC and battery RAM The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down mode. On the LPC2388, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider based on the APB clock ...
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... PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy. Upon power-up or any chip reset, the LPC2388 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.25.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL ...
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... Power control The LPC2388 supports a variety of power control features. There are three special modes of processor power reduction: Idle mode, Sleep mode, and Power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value ...
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... When it times out, access to the flash will be allowed. The customers need to reconfigure the PLL and clock dividers accordingly. 7.25.4.4 Power domains The LPC2388 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the Battery RAM. On the LPC2388, I/O pads are powered by the 3 ...
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... System control 7.26.1 Reset Reset has four sources on the LPC2388: the RESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable ...
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... NXP Semiconductors 7.26.3 Code security (Code Read Protection - CRP) This feature of the LPC2388 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. ...
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... NXP Semiconductors 7.27 Emulation and debugging The LPC2388 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself ...
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... lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2388 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory. ...
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... I/O pins 0.5 [4] per supply pin - [4] per ground pin - [5] 65 based on package - heat transfer, not device power consumption [6] human body 2 000 model; all pins Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip Max Unit 3.6 V 3.6 V +4.6 V +4.6 V +4.6 V +5 DD(3V3) 0.5 ...
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... [ 0 DD(3V3 DDA [ 15 I [8] V < V < DD(3V3) I Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip [1] Typ Max 3.3 3.6 3.3 3.6 3.3 3.6 3.3 3.6 3.3 V DDA - 100 - 5 DD(3V3 0.8 0 DD(3V3 ...
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... CCLK = 72 MHz - DD(DCDC)(3V3 amb [ OLS [10 DD(3V3 < V < 3 Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip [1] Typ Max Unit 125 - mA 150 DD(3V3) - 0.3V V DD(3V3) 0.5V ...
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... GND L pin to GND with 33 : series resistor; steady state drive SoftConnect = ON drops below 1 grounded. DD(3V3 unless otherwise specified; ADC frequency 4.5 MHz. Conditions [1][2][3] [1][4] [1][5] [1][6] [1][7] [8] Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip [1] Min Typ Max 0 0.8 - 2.5 0 0.18 2 [11] ...
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... T ADC and the ideal transfer curve. See [8] See Figure 5. LPC2388_0 Preliminary data sheet Figure 4. Figure 4. Figure 4. Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip Figure 4. © NXP B.V. 2008. All rights reserved ...
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... Fig 4. ADC characteristics LPC2388_0 Preliminary data sheet (2) (5) (4) (3) 1 LSB (ideal) 1018 1019 (LSB ) ia ideal 1 LSB = Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip offset gain error error (1) 1020 1021 1022 1023 1024 V − V DDA SSA 1024 002aab136 © ...
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... NXP Semiconductors AD0[y] SAMPLE Fig 5. Suggested ADC interface - LPC2388 AD0[y] pin LPC2388_0 Preliminary data sheet LPC2378 R vsi 20 kΩ AD0[ Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip V EXT 002aac610 © NXP B.V. 2008. All rights reserved ...
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... EOP; see Figure 7 over specified ranges. DD(3V3) Conditions Min cy(clk) T cy(clk 0 qC; - amb measured in SPI Master mode; see Figure 8 Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip Min Typ Max Unit 8.5 - 13.8 ns 7 109 % 1.3 - 2.0 V 160 - 175 ...
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... Preliminary data sheet + 0 − 0 CHCL CLCX crossover point extended + t PERIOD FDEOP t su(SPI_MISO) Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip t CHCX t CLCH T cy(clk) 002aaa907 source EOP width: t FEOPT receiver EOP width: t EOPR1 002aab561 sampling edges 002aad326 © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC23XX Fig 9. LPC2388 USB interface on a self-powered device LPC23XX Fig 10. LPC2388 USB interface on a bus-powered device LPC2388_0 Preliminary data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1.5 kΩ V BUS Ω USB_D Ω ...
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... RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC2388 USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 11. LPC2388 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2388_0 Preliminary data sheet RESET_N ADR/PSW OE_N/INT_N V DD ...
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... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC2388 USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 12. LPC2388 USB OTG port configuration: VP_VM mode LPC2388_0 Preliminary data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1301 ADR/PSW SPEED SUSPEND SCL SDA INT_N ...
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... USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC2388 USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 V BUS Fig 13. LPC2388 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2388_0 Preliminary data sheet Ω 33 Ω 15 kΩ 15 kΩ ENA FLAGA 5 V OUTA ...
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... USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC2388 USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 14. LPC2388 USB OTG port configuration: USB port 1 host, USB port 2 host LPC2388_0 Preliminary data sheet Ω 33 Ω 15 kΩ 15 kΩ ENA FLAGA OUTA 5 V ...
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... scale (1) ( 0.20 20.1 20.1 22.15 22.15 1 0.5 0.09 19.9 19.9 21.85 21.85 REFERENCES JEDEC JEITA MS-026 Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip SOT486 detail X (1) ( θ 0.75 1.4 1.4 7 0.2 0.08 0.08 o 0.45 1.1 1.1 0 EUROPEAN ...
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... Reduced Media Independent Interface Request To Send Single Ended Zero Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... RSTOUT pin description updated: This is a 3.3 V pin. LPC2388_0.01 <tbd> LPC2388_0 Preliminary data sheet Data sheet status Change notice Preliminary data sheet Preliminary data sheet Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip Supersedes LPC2388_0.01 © NXP B.V. 2008. All rights reserved ...
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... I C-bus — logo is a trademark of NXP B.V. SoftConnect — trademark of NXP B.V. GoodLink — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip © NXP B.V. 2008. All rights reserved ...
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... Static characteristics . . . . . . . . . . . . . . . . . . . 39 10 Dynamic characteristics 10.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 Application information . . . . . . . . . . . . . . . . . 47 11.1 Suggested USB interface solutions . . . . . . . . 47 12 Package outline Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 53 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 54 15 Legal information . . . . . . . . . . . . . . . . . . . . . . 55 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 55 Rev. 00.02 — 28 January 2008 LPC2388 Fast communication chip continued >> © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 January 2008 Document identifier: LPC2388_0 LPC2388 All rights reserved. ...