ST62T25CB6 STMicroelectronics, ST62T25CB6 Datasheet - Page 27
ST62T25CB6
Manufacturer Part Number
ST62T25CB6
Description
IC MCU 8BIT OTP 4K 28 PDIP
Manufacturer
STMicroelectronics
Series
ST6r
Specifications of ST62T25CB6
Core Processor
ST6
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, WDT
Number Of I /o
20
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Data Converters
A/D 16x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
ST62T2x
Core
ST6
Data Bus Width
8 bit
Data Ram Size
64 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
20
Number Of Timers
1
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, ST622XC-KIT/110, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 8-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-2100-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST62T25CB6
Manufacturer:
ST
Quantity:
310
Company:
Part Number:
ST62T25CB6
Manufacturer:
STMicroelectronics
Quantity:
5
6 INTERRUPTS
The ST6 core may be interrupted by four maska-
ble interrupt sources, in addition to a Non Maska-
ble Interrupt (NMI) source. The interrupt process-
ing flowchart is shown in
Maskable interrupts must be enabled by setting
the GEN bit in the IOR register. However, even if
they are disabled (GEN bit = 0), interrupt events
are latched and may be processed as soon as the
GEN bit is set.
Each source is associated with a specific Interrupt
Vector, located in Program space (see
Mapping
table). In the vector location, the user
Figure
18.
Interrupt
must write a Jump instruction to the associated in-
terrupt service routine.
When an interrupt source generates an interrupt
request, the PC register is loaded with the address
of the interrupt vector, which then causes a Jump
to the relevant interrupt service routine, thus serv-
icing the interrupt.
Interrupts are triggered by events either on exter-
nal pins, or from the on-chip peripherals. Several
events can be ORed on the same interrupt vector.
On-chip peripherals have flag registers to deter-
mine which event triggered the interrupt.
ST6215C ST6225C
27/105
1