ST72F264G2M6 STMicroelectronics, ST72F264G2M6 Datasheet - Page 45

• Manufacturer Part Number: ST72F264G2M6
• Description: IC MCU 8BIT 8K 28 SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F264G2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: ST72F2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7F264-IND/USB, ST72F34X-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: ST7
• No. Of I/o's: 22
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: 497-6423 - BOARD EVAL BASED ON ST72264G1497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-2106-5

10 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external in-
terrupts or the I/O alternate functions.
10.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the ISxx bits of the Miscellaneous register and the
OPTION BYTE. This control allows you to have
two fully independent external interrupt source
sensitivities with configurable sources (using the
EXTIT option bit) as shown in
ure
Each external interrupt source can be generated
on four different events on the pin:
■
■
■
■
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I[1:0] bits in the CC register are set to 1
(interrupt masked). See
REGISTER DESCRIPTION" on page 43
tion 10.3 "MISCELLANEOUS REGISTER DE-
SCRIPTION" on page 46
programming.
10.2 I/O PORT ALTERNATE FUNCTIONS
The MISCR registers manage four I/O port miscel-
laneous alternate functions:
■
■
These functions are described in detail in the
tion 10.3 "MISCELLANEOUS REGISTER DE-
SCRIPTION" on page
– SS pin internal control to use the PB7 I/O port
– Master output capability on the MOSI pin
– Slave output capability on the MISO pin (PB5)
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Main clock signal (f
SPI pin configuration:
30.
function while the SPI is active.
(PB4) deactivated while the SPI is active.
deactivated while the SPI is active.
CPU
46.
) output on PC2
Section 9.8 "I/O PORT
for more details on the
Figure 29
and
and
Sec-
Sec-
Fig-
Figure 29. Ext. Interrupt Sensitivity (EXTIT=0)
Figure 30. Ext. Interrupt Sensitivity (EXTIT=1)
PC5
PC0
PA7
PA0
PB7
PB0
PC5
PC0
PA7
PA0
PB7
PB0
ST72260Gx, ST72262Gx, ST72264Gx
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
SOURCE
SOURCE
SOURCE
SOURCE
ei0
ei1
ei0
ei1
SENSITIVITY
SENSITIVITY
IS00
IS10
SENSITIVITY
SENSITIVITY
IS00
IS10
CONTROL
CONTROL
CONTROL
CONTROL
MISCR1
MISCR1
MISCR1
MISCR1
IS01
IS11
IS01
IS11
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