CY8CLED03D02-56LTXI Cypress Semiconductor Corp, CY8CLED03D02-56LTXI Datasheet
CY8CLED03D02-56LTXI
Specifications of CY8CLED03D02-56LTXI
Available stocks
Related parts for CY8CLED03D02-56LTXI
CY8CLED03D02-56LTXI Summary of contents
Page 1
... Type 2) System Resets PSoC SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 PowerPSoC™ Intelligent LED Driver ❐ 12-bit incremental ADCs ❐ 9-bit DACs ❐ Programmable gain amplifiers ❐ Programmable filters and comparators ❐ 32-bit timers and counters ❐ ...
Page 2
... Global Digital Interconnect SRAM 1K Interrupt Controller DIGITAL SYSTEM Digital Block Array Digital 2 MACs Clocks Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 DAC0 Hysteretic Mode DAC1 Controller 0 DAC2 Hysteretic Mode DAC3 Controller 1 DAC4 Hysteretic Mode DAC5 Controller 2 DAC6 Hysteretic Mode ...
Page 3
... CSN2 FN0[0,1,2, Global Digital Interconnect SRAM 1K Interrupt Controller DIGITAL SYSTEM Digital 2 MACs Clocks Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 DAC0 Hysteretic Mode DAC1 Controller 0 DAC2 Hysteretic Mode DAC3 Controller 1 DAC4 Hysteretic Mode DAC5 Controller 2 Digital Mux Analog Mux ...
Page 4
... CSN2 CSA3 CSP3 CSN3 FN0[0,1,2,3] 4 Global Digital Interconnect SRAM Interrupt Controller DIGITAL SYSTEM Digital Clocks Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 DAC0 Hysteretic Mode DAC1 Controller 0 DAC2 Hysteretic Mode DAC3 Controller 1 DAC4 Hysteretic Mode DAC5 Controller 2 DAC6 ...
Page 5
... CSA2 CSP2 CSN2 FN0[0,1,2,3] 4 Global Digital Interconnect SRAM 1K Interrupt Controller DIGITAL SYSTEM Digital Clocks Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 DAC0 Hysteretic Mode DAC1 Controller 0 DAC2 Hysteretic Mode DAC3 Controller 1 DAC4 Hysteretic Mode DAC5 Controller 2 Digital Mux ...
Page 6
... Four independent channels ■ DAC configurable thresholds ■ Wide switching frequency range from 20 kHz to 2 MHz Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 ■ Programmable minimum on and off time ■ Floating load buck, boost, and floating load buck-boost programmable topology controller The PowerPSoC contains four hysteretic controllers ...
Page 7
... Clocking MHz Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 The DMM modulator consists of a 12-bit PWM block and a 4-bit DSM (Delta Sigma Modulator) block. The width of the PWM, the width of the DMM, and the clock defines the output frequency. ...
Page 8
... These are used to set trip points which enable over voltage, over current, and other system event detection. Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 4.8 Built-in Switching Regulator The switching regulator is used to power the low voltage (5V portion of the PowerPSoC) from the input line ...
Page 9
... External Controller 0 Gate Drive 0 DAC1 . FN0( FN0(2) FN0(3) DAC6 Hysteretic Mode External Controller 3 Gate Drive 3 DAC7 Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Figure 4-6. PowerPSoC in Master/Slave Configuration PPSoC (Master sense - . { . . Figure 4-7. Event Detection External FET GD 0 Event Detect FN0(0) ...
Page 10
... This configurability frees your designs from the constraints of a fixed peripheral controller. Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 There are four digital blocks in each row. This allows optimum choice of system resources for your application. Figure 5-1. Digital System Block Diagram ...
Page 11
... Notes. In general, and unless otherwise noted in the relevant application notes, the minimum signal-to-noise ratio (SNR) for CapSense applications is 5:1. Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 5.4 Additional System Resources System resources provide additional capability useful in complete systems. Additional resources include a multiplier, P0[4] decimator, low voltage detection, and power on reset ...
Page 12
... Figure 6-2. LED Lighting with RGBA Color Mixing Driving External MOSFETS as Floating Load Buck Converter SENSE Dual mode Gate Drive 1 Hysteretic PWM References Dim Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 SENSE SENSE Hysteretic Hysteretic Hysteretic PWM PWM ...
Page 13
... Figure 6-3. LED Lighting with a Single Channel Boost Driving Three Floating Load Buck Channels Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 SENSE R R SENSE SENSE Hysteretic Hysteretic Hysteretic PWM PWM PWM Hysteretic Hysteretic Hysteretic Dim Dim Dim references ...
Page 14
... CY8CLED04D02-56LTXI 4X0.5A 4 CY8CLED04G01-56LTXI 0 4 CY8CLED03D01-56LTXI 3X1.0A 3 CY8CLED03D02-56LTXI 3X0.5A 3 CY8CLED03G01-56LTX Getting Started The quickest way to understand the PowerPSoC device is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PowerPSoC integrated circuit and presents specific pin, register, and electrical specifications ...
Page 15
... USB port. The base unit is universal and operates with all PowerPSoC devices. Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 10. Designing with User Modules The development process for the PowerPSoC device differs from that of a traditional fixed function microprocessor. The ...
Page 16
... In-Circuit Emulator IDE Integrated Development Environment ILO Internal Low-speed Oscillator IMO Internal Main Oscillator ISSP In-System Serial Programming Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Acronym Description I/O Input/Output IPOR Imprecise Power On Reset LED Light Emitting Diode LSB ...
Page 17
... SW0 Power Switch GD0 External Low Side Gate Driver 0 42 PGND0 Power FETGround 0 43 GDVSS Gate Driver Ground Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Figure 12-1. CY8CLED04D0x 56-Pin PowerPSoC Device Description P1[0] 1 P2[2] 2 P0[3] 3 P0[5] 4 P0[7] 5 P1[1] ...
Page 18
... Digital Ground Connect 41 O GD0 External Low Side Gate Driver 0 42 VSS Digital Ground 43 GDVSS Gate Driver Ground Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Figure 12-2. CY8CLED04G01 56-Pin PowerPSoC Device Description P1[0] 1 P2[2] 2 P0[3] 3 P0[5] 4 P0[7] 5 P1[1] 6 ...
Page 19
... SW0 Power Switch GD0 External Low Side Gate Driver 0 42 PGND0 Power FET Ground 0 43 GDVSS Gate Driver Ground Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Figure 12-3. CY8CLED04DOCD 56-Pin PowerPSoC Device Description P1[0] 1 P2[2] 2 P0[3] 3 P0[5] 4 P0[7] 5 ...
Page 20
... CY8CLED03D0x 56-Pin Part Pinout (without OCD) The CY8CLED03D01 and CY8CLED03D02 PowerPSoC devices are available with the following pinout information. Every port pin (labeled with a “P” and “FN0”) is capable of Digital I/O. Table 12-4. CY8CLED03D0x 56-Pin Part Pinout (QFN) Type ...
Page 21
... Gate Driver Ground Connect 41 O GD0 External Low Side Gate Driver 0 42 VSS Digital Ground 43 GDVSS Gate Driver Ground Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Figure 12-5. CY8CLED03G01 56-Pin PowerPSoC Device Description P1[0] 1 P2[2] 2 P0[3] 3 P0[5] 4 P0[7] 5 P1[1] 6 ...
Page 22
... Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 13.2 Register Naming Conventions The register naming convention specific to the PSoC core section of PowerPSoC blocks and their registers is: <Prefix>mn<Suffix> where m = row index column index Therefore, ASD13CR3 is a register for an analog PowerPSoC block in row 1 column 3 ...
Page 23
... DCB12DR0 38 # DPWM0PCFG DCB12DR1 39 W DPWM1PCFG DCB12DR2 3A RW DPWM2PCFG DCB12CR0 3B # DPWM3PCFG DCB13DR0 3C # DPWMINTFLG DCB13DR1 3D W DPWMINTMSK DCB13DR2 3E RW DPWMSYNC DCB13CR0 3F # Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Addr Addr Access Name Access (0,Hex) (0,Hex ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 84 ...
Page 24
... DBB01OU 36 RW ACB01CR1 37 ACB01CR2 DCB12FN 38 RW DCB12IN 39 RW GDRV0_CR DCB12OU GDRV1_CR DCB13FN 3C RW DCB13IN 3D RW GDRV2_CR DCB13OU GDRV3_CR Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Addr Addr Access Name Access (1,Hex) (1,Hex ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ...
Page 25
... NEVER exceeded. Functional operation is not implied under any conditions beyond the “Electrical Characteristics”, listed page 27 onwards. Extended exposure to “Absolute Maximum Ratings” may affect device reliability. Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Specifications are valid for -40°C ≤ T Symbol ...
Page 26
... Operating Temperature Symbol Description T Ambient Temperature A T Junction Temperature J Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Figure 14-1. High Voltage Supply Ramp Time Vin 1 Min Typ Max -40 – +85 -40 – +115 32V 7V µs Units Notes ≤ 115°C ° ...
Page 27
... IMO = 24 MHz I Supply Current(AVDD pin) AVDD I Supply Current Per Channel(GDVDD GDVDD pins) I Sleep (Mode) Current with POR, LVD, SB Sleep Timer, and WDT. Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ Max Units 0.02 – 2 MHz – – 100 ns ...
Page 28
... DSS I Supply Current Per Channel - FET (Internal SFET Gate Driver) Note 2. See the individual user module data sheets for information on maximum frequencies for user modules. Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ Max Units 23.04 24 24.96 MHz 0 ...
Page 29
... Driver Table 15-7. Power FET Driver AC Specifications Symbol Description t Rise Time r t Fall Time f tp(LH) Propagation Delay (Low-to-High) tp(HL) Propagation Delay (High-to-Low)) Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ Max Units – – – – DSS, R ...
Page 30
... Supply Current - Comparator SCOMP V Input Common Mode Voltage Range ICM Table 15-11. Comparator AC Specifications Symbol Description t Comparator Delay Time (FN0x pin to FN0x D pin) Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ Max Units 1V ≤ V – – 7 ≤ V – – ...
Page 31
... CSN Input Capacitance IN_CSN Table 15-13. Current Sense Amplifier AC Specifications Symbol Description t Output Settling Time Final Value SETTLE t Power Up Time Final Value POWERUP Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Figure 15-3. Comparator Timing Diagram Min Typ Max 7 – – – ...
Page 32
... PrISM Mode f PrISM Output Frequency RANGE Range DMM Mode f DMM Dimming Frequency RANGE,Dimming Range f DMM Dither Frequency Range RANGE,Dither Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 IN V CSP V CSN t SETTLE t DELAY t POWERUP OUT Not Valid Min Typ – ...
Page 33
... DS(ON),PFET Line Line Regulation REG Load Load Regulation REG PSRR Power Supply Rejection Ratio E Built-in Switching Regulator Efficiency BSR Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ Max Units μA – – 600 Mode 0 and Mode1 -1 – 1 ...
Page 34
... Mode Table 15-20. Built-in Switching Regulator Recommended Components Component Name R fb1 R fb2 C comp R comp L R sense Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ Max 0.956 1 1.04 – 10 – – – 1 – – 100 1 – – – ...
Page 35
... Figure 15-5. Built-in Switching Regulator Timing Diagram V REGIN Powerdown MODE Ref Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 V REGIN REGOUT Time HVDD PD PD_ACT Figure 15-6. Built-in Switching Regulator Osc Error Amplifier SREGHVIN Logic and Gate Drive Comparator L SREGSW ...
Page 36
... Rise Time, Normal Strong Mode, Cload = 50 pF tFallF Fall Time, Normal Strong Mode, Cload = 50 pF tRiseS Rise Time, Slow Strong Mode, Cload = 50 pF tFallS Fall Time, Slow Strong Mode, Cload = 50 pF Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ Max 4 5.6 4 5.6 VDD - 1.0 – ...
Page 37
... Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRR Supply Voltage Rejection Ratio OA Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ Max Units – 1 ...
Page 38
... LPC supply current SLPC V LPC voltage offset OSLPC Table 15-26. Low Power Comparator AC Specifications Symbol Description t LPC response time RLPC Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ Max Units μs – – 3.9 μs – – ...
Page 39
... Small Signal Bandwidth, 20mV OBSS 100 pF Load Power = Low Power = High BW Large Signal Bandwidth, 1V OBLS pp 100 pF Load Power = Low Power = High Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ – 3 – +6 0.5 – VDD - 1.0 – 0.6 – ...
Page 40
... Table 15-30. Analog Block DC Specifications Symbol Description R Resistor Unit Value (Continuous Time Capacitor Unit Value (Switched SC Capacitor) Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ 1.28 1.30 VDD/2 - 0.04 VDD/2 - 0.01 VDD/2 + 0.007 0.048 0.030 0.024 BG - 0.009 ...
Page 41
... AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V. 4. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 5. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ Max ...
Page 42
... For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ Max – ...
Page 43
... Maximum Input Clock Frequency Maximum Input Clock Frequency with VDD ≥ 4.75V, 2 Stop Bits Note minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Min Typ Max Units [7] 50 – ...
Page 44
... LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + t = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released. SUDATI2 Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 2 C SDA and SCL Pins Standard Mode Fast Mode ...
Page 45
... Table 16-1. Device Key Features and Ordering Information PowerPSoC Part Number No. of Pins CY8CLED04D01-56LTXI 56 QFN CY8CLED04D02-56LTXI 56 QFN CY8CLED04G01-56LTXI 56 QFN CY8CLED04DOCD-56LTXI 56 QFN CY8CLED03D01-56LTXI 56 QFN CY8CLED03D02-56LTXI 56 QFN CYCCLED03G01-56LTXI 56 QFN 17. Ordering Code Definitions LED0x xxx (xxxx xxxx Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Package Channels ...
Page 46
... Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 Refer to the solder manufacturer specifications. Document Number: 001-46319 Rev. *E CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Figure 18-1. 56-Pin (8x8 mm) QFN 19.1.1 PSoC Designer 5.0 At the core of the PSoC development software suite is PSoC Typical θ ...
Page 47
... Document History Page Document Title: CY8CLED04G01, CY8CLED03G01, CY8CLED03D01, CY8CLED03D02, CY8CLED04D01, CY8CLED04D02 PowerPSoC™ Intelligent LED Driver Document Number: 001-46319 Orig. of Submission Revision ECN No. Change ** 2506500 ANWA/ 5/20/2008 DSG *A 2575708 ANWA/ 10/01/08 AESA *B 2662774 KJV 2/19/2009 *C 2665155 KJV/PYRS 02/25/2009 *D 2671254 KJV/PYRS 03/10/2009 ...