CY8CLED03D02-56LTXI Cypress Semiconductor Corp, CY8CLED03D02-56LTXI Datasheet - Page 43

• Manufacturer Part Number: CY8CLED03D02-56LTXI
• Description: IC POWERPSOC 3CH 1A 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: PowerPSoC® CY8CLEDr

Specifications of CY8CLED03D02-56LTXI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: DALI, DMX512, I²C, IrDA, SPI, UART/USART
• Peripherals: LED, LVD, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-2882 - KIT STARTER POWERPSOC LIGHTING428-2281 - KIT EVAL POWERPSOC LIGHTING428-2271 - KIT EVAL COLOR-LOCK428-2270 - KIT STARTER DEMO LIGHTING770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 428-2925

15.19 PSoC Core Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and T
Table 15-34. Digital Block AC Specifications
Document Number: 001-46319 Rev. *E
Note
Timer
Counter
Dead Band Kill Pulse Width:
CRCPRS
(PRS Mode)
CRCPRS
(CRC Mode)
SPIM
SPIS
Transmitter Maximum Input Clock Frequency
Receiver
7. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Function
J
≤ 115°C. Typical parameters apply to 5V at 25°C. These are for design guidance only.
Capture Pulse Width
Maximum Frequency, No Capture
Maximum Frequency, With Capture
Enable Pulse Width
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
Maximum Frequency
Maximum Input Clock Frequency
Maximum Input Clock Frequency
Maximum Input Clock Frequency
Maximum Input Clock Frequency
Width of SS_ Negated Between
Transmissions
Maximum Input Clock Frequency with VDD
≥ 4.75V, 2 Stop Bits
Maximum Input Clock Frequency
Maximum Input Clock Frequency with VDD
≥ 4.75V, 2 Stop Bits
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
Description
50
50
50
50
50
Min
20
–
–
–
–
–
–
–
–
–
–
–
–
–
[7]
[7]
[7]
[7]
[7]
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CY8CLED04G01, CY8CLED03G01
CY8CLED04D01, CY8CLED04D02
CY8CLED03D01, CY8CLED03D02
49.92
24.96
49.92
24.96
49.92
49.92
24.96
24.96
49.92
24.96
49.92
Max
8.32
4.16
–
–
–
–
–
–
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
Maximum data rate at 4.1 MHz due to
2 x over clocking.
Maximum data rate at 3.08 MHz due
to 8 x over clocking.
Maximum data rate at 6.15 MHz due
to 8 x over clocking.
Maximum data rate at 3.08 MHz due
to 8 x over clocking.
Maximum data rate at 6.15 MHz due
to 8 x over clocking.
Notes
Page 43 of 47
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