EZ80F91NAA50EG Zilog, EZ80F91NAA50EG Datasheet - Page 147

• Manufacturer Part Number: EZ80F91NAA50EG
• Description: IC ACCLAIM MCU 256KB 144BGA
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91NAA50EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG, eZ80F910200KITG
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4565

PS027001-0707
Timer Reload Register—High Byte
The Timer x Reload Register—High Byte (see
(MSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is
reloaded into the timer upon end-of-count. When the reload bit (TMRx_CTL[RLD]) is set
to 1, it forces the reload function, the timer reload value is written to the timer on the next
rising edge of the clock.
This register shares its address with the corresponding timer data register.
Table 60. Timer Reload Register—High Byte
TMR1_RR_H = 0069h, TMR2_RR_H = 0073h, TMR3_RR_H = 0078h)
Timer Input Capture Control Register
The Timer x Input Capture Control Register (see
edges to be captured. For Timer 1, CAP_EDGE_B is used for IC1 and CAP_EDGE_A is
for IC0. For Timer 3, CAP_EDGE_B is for IC3, and CAP_EDGE_A is for IC2.
Table 61. Timer Input Capture Control Register
(TMR1_CAP_CTL = 006Ah, TMR3_CAP_CTL = 007Bh)
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:0]
TMR_RR_H
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:4]
Value
00h–FFh
Value
0000
R/W
W
7
0
7
0
Description
These bits represent the High byte of the 2-byte timer
reload value, {TMR
is bit 15 (msb) of the 16-bit timer reload value. Bit 0 is bit 8
of the 16-bit timer reload value.
Description
Reserved
R/W
W
6
0
6
0
R/W
W
5
0
5
0
Table
Table
x
_RR_H[7:0], TMR
R/W
W
4
0
4
0
60) stores the most-significant byte
(TMR0_RR_H = 0064h,
61) is used to select the edge or
R/W
W
3
0
3
0
Programmable Reload Timers
Product Specification
R/W
W
2
0
x
2
0
_RR_L[7:0]}. Bit 7
eZ80F91 ASSP
R/W
W
1
0
1
0
R/W
W
0
0
0
0
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