EZ80F91NAA50EG Zilog, EZ80F91NAA50EG Datasheet - Page 93
![IC ACCLAIM MCU 256KB 144BGA](/photos/12/15/121561/ez80f91naa50eg_sml.jpg)
EZ80F91NAA50EG
Manufacturer Part Number
EZ80F91NAA50EG
Description
IC ACCLAIM MCU 256KB 144BGA
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91NAA50EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG, eZ80F910200KITG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4565
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 27. Chip Select x Lower Bound Register
CS2_LBR = 00AEh, CS3_LBR = 00B1h)
PS027001-0707
Bit
CS0_LBR Reset
CS1_LBR Reset
CS2_LBR Reset
CS3_LBR Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
CSX_LBR
Chip Select Registers
Value Description
00h–
FFh
Chip Select x Lower Bound Register
For Memory chip selects, the chip select x Lower Bound register (see
the lower bound of the address range for which the corresponding Memory chip select (if
enabled) is active. For I/O chip selects, the chip select x Lower Bound register defines the
address to which ADDR[15:8] is compared to generate an I/O chip select. All chip select
lower bound registers reset to
For Memory Chip Selects (CSx_IO = 0)
This byte specifies the lower bound of the chip select address
range. The upper byte of the address bus, ADDR[23:16], is
compared to the values contained in these registers for
determining whether a Memory chip select signal must be
generated.
For I/O Chip Selects (CSx_IO = 1)
This byte specifies the chip select address value. ADDR[15:8] is
compared to the values contained in these registers for
determining whether an I/O chip select signal must be generated.
R/W
7
0
0
0
0
R/W
6
0
0
0
0
R/W
5
0
0
0
0
00h
.
R/W
4
0
0
0
0
(CS0_LBR = 00A8h, CS1_LBR = 00ABh,
R/W
3
0
0
0
0
R/W
2
0
0
0
0
R/W
1
0
0
0
0
Chip Selects and Wait States
Product Specification
R/W
0
0
0
0
0
Table
eZ80F91 ASSP
27) defines
85
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