EZ80F91NAA50EG Zilog, EZ80F91NAA50EG Datasheet - Page 283
![IC ACCLAIM MCU 256KB 144BGA](/photos/12/15/121561/ez80f91naa50eg_sml.jpg)
EZ80F91NAA50EG
Manufacturer Part Number
EZ80F91NAA50EG
Description
IC ACCLAIM MCU 256KB 144BGA
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91NAA50EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG, eZ80F910200KITG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4565
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 155. PLL Control Register 1
.
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:6]
5
LCK_STATUS
4
INT_LOCK
3
INT_UNLOCK
2
INT_LOCK_EN
1
INT_UNLOCK_
EN
0
PLL_ENABLE
Note
1. PLL cannot be disabled if the CLK_MUX bit of PLL_CTL0[1:0] is set to 01, because the PLL is
selected as the clock source.
Value Description
00
0
1
0
1
0
1
0
1
0
1
0
1
Reserved.
PLL is currently out of lock.
PLL is currently locked.
Lock signal from PLL has not risen since last time register was
read.
Interrupt generated when PLL enters LOCK mode. Held until
register is read.
Lock signal from PLL has not fallen since last time register was
read
Interrupt generated when PLL goes out of lock. Held until
register is read.
Interrupt generation for PLL locked condition (Bit 4) is disabled.
Interrupt generation for PLL locked condition is enabled.
Interrupt generation for PLL unlocked condition (Bit 3) is
disabled.
Interrupt generation for PLL unlocked condition is enabled.
PLL is disabled.
PLL is enabled.
R
7
0
R
6
0
(PLL_CTL1 = 005Fh)
1
R
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
Product Specification
R/W
0
0
Phase-Locked Loop
eZ80F91 ASSP
275
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