C8051F501-IQ Silicon Laboratories Inc, C8051F501-IQ Datasheet - Page 213

• Manufacturer Part Number: C8051F501-IQ
• Description: IC 8051 MCU 64K FLASH 48-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F501-IQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 48-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Package: 48PQFP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1512

LIN Register Definition 21.6. LIN0ST: LIN0 Status Register
Indirect Address = 0x09
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
WAKEUP
ACTIVE
ERROR
DTREQ
ABORT
LININT
DONE
Name
ACTIVE
IDLT
R
7
0
LIN Active Indicator Bit.
0: No transmission activity detected on the LIN bus.
1: Transmission activity detected on the LIN bus.
Bus Idle Timeout Bit. (slave mode only)
0: The bus has not been idle for four seconds.
1: No bus activity has been detected for four seconds, but the bus is not yet in Sleep
mode.
Aborted Transmission Bit. (slave mode only)
0: The current transmission has not been interrupted or stopped. This bit is reset to 0
after receiving a SYNCH BREAK that does not interrupt a pending transmission.
1: New SYNCH BREAK detected before the end of the last transmission or the STOP
bit (LIN0CTRL.7) has been set.
Data Request Bit. (slave mode only)
0: Data identifier has not been received.
1: Data identifier has been received.
Interrupt Request Bit.
0: An interrupt is not pending. This bit is cleared by setting RSTINT (LIN0CTRL.3)
1: There is a pending LIN0 interrupt.
Communication Error Bit.
0: No error has been detected. This bit is cleared by setting RSTERR (LIN0CTRL.2)
1: An error has been detected.
Wakeup Bit.
0: A wakeup signal is not being transmitted and has not been received.
1: A wakeup signal is being transmitted or has been received
Transmission Complete Bit.
0: A transmission is not in progress or has not been started. This bit is cleared at the
start of a transmission.
1: The current transmission is complete.
IDLTOUT
R
6
0
ABORT
R
5
0
DTREQ
Rev. 1.2
R
4
0
Function
LININT
R
3
0
C8051F50x/F51x
ERROR
R
2
0
WAKEUP
R
1
0
DONE
R
0
0
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