MC9S08AW60CFGE Freescale Semiconductor, MC9S08AW60CFGE Datasheet - Page 225
![IC MCU 64K FLASH 44-LQFP](/photos/12/17/121739/mc9s08aw60cfde_sml.jpg)
MC9S08AW60CFGE
Manufacturer Part Number
MC9S08AW60CFGE
Description
IC MCU 64K FLASH 44-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AW32CFDE.pdf
(324 pages)
Specifications of MC9S08AW60CFGE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
S08AW
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
8
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AW60E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
DEMO9S08AW60E - DEMO BOARD FOR MC9S08AW60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08AW60CFGE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S08AW60CFGER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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13.4
This section provides a complete functional description of the IIC module.
13.4.1
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system
communication is described briefly in the following sections and illustrated in
Freescale Semiconductor
SDA
SCL
SDA
SCL
•
•
•
•
SIGNAL
SIGNAL
START
START
START signal
Slave address transmission
Data transfer
STOP signal
MSB
MSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Functional Description
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
1
1
IIC Protocol
2
2
CALLING ADDRESS
CALLING ADDRESS
3
3
4
4
5
5
6
6
Figure 13-8. IIC Bus Transmission Signals
7
7
READ/
WRITE
READ/
WRITE
LSB
LSB
8
8
MC9S08AW60 Data Sheet, Rev 2
ACK
ACK
BIT
BIT
9
9
XX
REPEATED
SIGNAL
XXX
START
MSB
MSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
D7
1
1
D6
2
2
NEW CALLING ADDRESS
D5
3
3
DATA BYTE
D4
4
4
D3
Chapter 13 Inter-Integrated Circuit (S08IICV1)
5
5
D2
6
6
D1
7
7
Figure
READ/
WRITE
LSB
LSB
D0
8
8
ACK
BIT
NO
ACK
NO
BIT
9
9
13-8.
SIGNAL
SIGNAL
STOP
STOP
225
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