MC9S08AW60CFGE Freescale Semiconductor, MC9S08AW60CFGE Datasheet - Page 300
![IC MCU 64K FLASH 44-LQFP](/photos/12/17/121739/mc9s08aw60cfde_sml.jpg)
MC9S08AW60CFGE
Manufacturer Part Number
MC9S08AW60CFGE
Description
IC MCU 64K FLASH 44-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AW32CFDE.pdf
(324 pages)
Specifications of MC9S08AW60CFGE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
S08AW
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
8
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AW60E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
DEMO9S08AW60E - DEMO BOARD FOR MC9S08AW60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08AW60CFGE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S08AW60CFGER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Appendix A Electrical Characteristics and Timing Specifications
A.10
This section describes ac timing characteristics for each peripheral system. For detailed information about
how clocks for the bus are generated, see
A.10.1
300
1
2
3
4
5
Num
Typical values are based on characterization data at V
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
When any reset is initiated, internal circuitry drives the reset pin low for about 34 bus cycles and then samples the level on
the reset pin about 38 bus cycles later to distinguish external reset requests from internal requests.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% V
1
2
4
6
8
3
5
7
9
AC Characteristics
C
P
T
Control Timing
Bus frequency (t
Real-time interrupt internal oscillator period
External reset pulse width
(t
Reset low drive
Active background debug mode latch setup time
Active background debug mode latch hold time
IRQ pulse width
KBIPx pulse width
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
cyc
Asynchronous path
Synchronous path
Asynchronous path
Synchronous path
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
Slew rate control enabled (PTxSE = 1)
Slew rate control disabled (PTxSE = 0)
= 1/f
Self_reset
3
cyc
)
Parameter
= 1/f
4
3
2
2
Bus
DD
2
)
MC9S08AW60 Data Sheet, Rev 2
and 80% V
Table A-13. Control Timing
Chapter 8, “Internal Clock Generator
DD
DD
levels. Temperature range –40°C to 125°C.
= 5.0V, 25°C unless otherwise stated.
5
t
t
t
t
Symbol
Rise
Rise
ILIH,
ILIH,
t
t
t
MSSU
t
rstdrv
f
extrst
t
MSH
Bus
RTI
, t
, t
t
t
IHIL
IHIL
Fall
Fall
t
1.5 x t
1.5 x t
34 x t
Self_reset
1.5 x
Min
700
100
100
dc
25
25
—
—
—
—
cyc
cyc
cyc
(S08ICGV4).”
Typ
—
—
—
40
75
11
35
1
Freescale Semiconductor
1300
Max
20
—
—
—
—
—
—
—
—
—
—
MHz
Unit
μs
ns
ns
ns
ns
ns
ns
ns
ns
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