MC9S08AW60CFGE Freescale Semiconductor, MC9S08AW60CFGE Datasheet - Page 244
![IC MCU 64K FLASH 44-LQFP](/photos/12/17/121739/mc9s08aw60cfde_sml.jpg)
MC9S08AW60CFGE
Manufacturer Part Number
MC9S08AW60CFGE
Description
IC MCU 64K FLASH 44-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AW32CFDE.pdf
(324 pages)
Specifications of MC9S08AW60CFGE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
S08AW
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
8
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AW60E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
DEMO9S08AW60E - DEMO BOARD FOR MC9S08AW60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08AW60CFGE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S08AW60CFGER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 14 Analog-to-Digital Converter (S08ADC10V1)
244
ADLSMP
ADICLK
ADLPC
MODE
Field
ADIV
6:5
3:2
1:0
7
4
Reset:
W
R
Low Power Configuration — ADLPC controls the speed and power configuration of the successive
approximation converter. This is used to optimize power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration: {FC31}The power is reduced at the expense of maximum clock speed.
Clock Divide Select — ADIV select the divide ratio used by the ADC to generate the internal clock ADCK.
Table 14-6
Long Sample Time Configuration — ADLSMP selects between long and short sample time. This adjusts the
sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
Conversion Mode Selection — MODE bits are used to select between 10- or 8-bit operation. See
Input Clock Select — ADICLK bits select the input clock source to generate the internal clock ADCK. See
Table
ADLPC
14-8.
7
0
shows the available clock configurations.
MODE
ADIV
00
01
10
11
00
01
10
11
Table 14-5. ADC1CFG Register Field Descriptions
Figure 14-10. Configuration Register (ADC1CFG)
0
6
ADIV
8-bit conversion (N=8)
Reserved
10-bit conversion (N=10)
Reserved
Table 14-6. Clock Divide Select
Table 14-7. Conversion Modes
MC9S08AW60 Data Sheet, Rev 2
0
5
Divide Ratio
1
2
4
8
ADLSMP
0
4
Mode Description
Description
0
3
MODE
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
Clock Rate
Input clock
0
2
Freescale Semiconductor
0
1
ADICLK
Table
0
0
14-7.
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