R5F212B7SNFP#U0 Renesas Electronics America, R5F212B7SNFP#U0 Datasheet - Page 476

• Manufacturer Part Number: R5F212B7SNFP#U0
• Description: IC R8C/2B MCU FLASH 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Br

Specifications of R5F212B7SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 16.50
16.3.6
The states of pins SCL and SDA are routed through the noise canceller before being latched internally.
Figure 16.50 shows a Block Diagram of Noise Canceller.
The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal
(or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next
circuit. When they do not match, the former value is retained.
f1 (sampling clock)
Nov 26, 2007
Noise Canceller
SCL or SDA
input signal
Block Diagram of Noise Canceller
Page 454 of 580
f1 (sampling clock)
Period of f1
D
Latch
C
Q
D
Latch
C
Q
16. Clock Synchronous Serial Interface
detection
Match
circuit
Internal SCL
or SDA signal