MC908AP32CBE Freescale Semiconductor, MC908AP32CBE Datasheet - Page 39

• Manufacturer Part Number: MC908AP32CBE
• Description: IC MCU 32K FLASH 8MHZ 42DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32CBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 30
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Controller Family/series: HC08
• No. Of I/o's: 30
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08AP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908AP64E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

#
Freescale Semiconductor
$FE0A
$FE0B
$FE0C
$FE0D
$FE0E
$FFCF
$FE06
$FE07
$FE08
$FE09
$FE0F
$FFFF
Addr.
MOR is a non-volatile FLASH register; write by programming.
LVI Status Register (LVISR)
Interrupt Status Register 3
Break Status and Control
FLASH Control Register
Register Name
COP Control Register
Mask Option Register
FLASH Block Protect
U = Unaffected
Break Address
Break Address
Register High
Register Low
(BRKSCR)
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 9)
(COPCTL)
Reserved
Reserved
Reserved
(FLBPR)
Register
Register
(BRKH)
(MOR)
(FLCR)
(BRKL)
(INT3)
#
Erased:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Reset:
Read:
Write:
X = Indeterminate
OSCSEL1 OSCSEL0
MC68HC908AP Family Data Sheet, Rev. 4
LVIOUT
BRKE
BPR7
Bit 15
Bit 7
Bit 7
R
R
R
R
U
0
0
0
0
0
0
0
0
0
1
BRKA
BPR6
IF21
14
R
R
R
R
U
6
0
0
0
0
0
6
0
0
0
1
0
BPR5
IF20
13
R
R
R
R
R
U
5
0
0
0
0
0
5
0
0
0
0
0
1
Writing clears COP counter (any value)
Low byte of reset vector
= Unimplemented
Unaffected by reset
BPR4
IF19
12
R
R
R
R
R
U
4
0
0
0
0
0
4
0
0
0
0
0
1
HVEN
BPR3
IF18
11
R
R
R
R
R
U
3
0
0
0
0
3
0
0
0
0
0
1
MASS
BPR2
IF17
10
R
R
R
R
R
U
R
2
0
0
0
0
2
0
0
0
0
0
1
= Reserved
ERASE
BPR1
IF16
R
R
R
R
R
U
1
0
0
0
9
0
1
0
0
0
0
0
1
Monitor ROM
BPR0
PGM
Bit 0
IF15
Bit 8
Bit 0
R
R
R
R
R
U
0
0
0
0
0
0
0
0
0
1
39