SCF5250LAG100 Freescale Semiconductor, SCF5250LAG100 Datasheet
SCF5250LAG100
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SCF5250LAG100 Summary of contents
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... Dhrystone 2.1 MIPS @ 120MHz performance at a very competitive price. The This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. Document Number: SCF5250EC Rev. SCF5250 Package Information MAPBGA– ...
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... DSP in certain applications. Most peripheral pins can also be remapped as General Purpose I/O pins. 1.1 Orderable Part Numbers Table 1 lists the orderable part numbers for the SCF5250 processor. Orderable Part Maximum Clock Number Frequency SCF5250LPV100 100 MHz SCF5250LAG100 100 MHz SCF5250PV120 120 MHz SCF5250AG120 120 MHz 1 SCF5250DAG120 120 MHz 2 SCF5250EAG120 ...
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... Mbits). The controller supports a 16-bit data bus. A unique addressing scheme allows for increases in system memory size without rerouting address lines and rewiring boards. The controller operates in page mode, non-page mode, and burst-page mode and supports SDRAMS. Freescale Semiconductor SCF5250 Data Sheet: Technical Data, Rev ...
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... The audio bus can also be used for audio format conversion. 1.2.12 CD-ROM Encoder/Decoder The SCF5250 is capable of processing CD-ROM sectors in hardware. Processing is compliant with CD-ROM and CD-ROM XA standards. 4 SCF5250 Data Sheet: Technical Data, Rev. 1.3 Freescale Semiconductor ...
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... The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is derived from the system clock. In addition to the ÷1 and ÷16 clock derived from the bus clock (CPU clock / 2), the programmable timer-output pins either generate an active-low pulse or toggle the outputs. Freescale Semiconductor SCF5250 Data Sheet: Technical Data, Rev ...
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... SDRAM and Flash accesses to propagate to the IDE bus. The control signals for the buffers are generated in the SCF5250. Low cost version SCF5250LPV100 and SCF5250LAG100 does not run production test for the IDE/CF/SD/MMC interfaces. Freescale does not guarantee these interfaces will work on these two devices ...
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... Voltage Regulator The SCF5250 contains an on-chip linear regulator that generates 1.2V from a 3.3V input. The regulator is self-contained and drives the 1.2V core voltage out on one pin that can be used to power the core supply Freescale Semiconductor SCF5250 Data Sheet: Technical Data, Rev ...
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... UART x2 ADC DMAs / Timers PLL GPI/O 128K SRAM V2 System ® ColdFire Bus Core Controller Figure 1. SCF5250 Block Diagram SCF5250 Data Sheet: Technical Data SPDIF Tx SPDIF Rx 1.2V Regulator Boot ROM Oscillator SDRAM Ctr & Chip Selects Rev. 1.3 Freescale Semiconductor ...
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... SCL0/SDATA1_BS1/GPIO41 SCL1/TXD1/GPIO10 Serial Data Line SDA0/SDATA3/GPIO42 SDA1/RXD1/GPIO44 Receive Data SDA1/RXD1/GPIO44 RXD0/GPIO46 Freescale Semiconductor Table 2. SCF5250 Signal Index Mnemonic 24 address lines, address line 23 multiplexed with GPO54 and address 24 is multiplexed with A20 (SDRAM access only). Bus write enable - indicates if read or write cycle in progress ...
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... Output Out Out In Out In Out In In/Out Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Out Out – Rev. 1.3 Freescale Semiconductor Reset State – – – – – – – – – – – – – – – – – – ...
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... High Impedance HI-Z Debug Data DDATA0/CTS1/SDATA0_SDIO1/GPIO1 DDATA1/RTS1/SDATA2_BS2/GPIO2 DDATA2/CTS0/GPIO3 DDATA3/RTS0/GPIO4 Freescale Semiconductor Table 2. SCF5250 Signal Index (continued) Mnemonic Secure Digital command lane Memory Stick interface 2 data I/O Clock out for both Memory Stick interfaces and for Secure Digital Memory Stick interface 1 data I/O ...
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... Multiplexed serial input for the JTAG or background debug module. Multiplexed serial output for the JTAG or background debug module. SCF5250 Data Sheet: Technical Data, Input/ Function Output In/Out Out Out Rev. 1.3 Freescale Semiconductor Reset State Hi-Z – – – – – – ...
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... Synchronous DRAM UDQM and LQDM signals Synchronous DRAM clock Synchronous DRAM Clock Enable Freescale Semiconductor Table 3. SDRAM Controller Signals The SDRAS/GPIO59 active low pin provides a seamless interface to the RAS input on synchronous DRAM The SDCAS/GPIO39 active low pin provides a seamless interface to CAS input on synchronous DRAM ...
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... The SDA0/SDATA3/GPIO42 and SDA1/RXD1/GPIO44 bidirectional signals are the data input/output for the first and second serial I Signals are multiplexed 14 Table 2 Table Module Signals Description module operation. The I C module controls this signal when the bus is in master interface. SCF5250 Data Sheet: Technical Data timing. Rev. 1.3 Freescale Semiconductor ...
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... Timer module signal which provides an external interface to Timer0. Serial Module Signal Timer Output The SDATAO1/TOUT0/GPIO18 programmable output pulse or toggle on various timer events. Freescale Semiconductor transfer serial data between the two UART modules and the external Table 5. Serial Module Signals Description Table 6 ...
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... I digital audio (IEC958) output. EBUOUT1 is digital audio out for consumer mode, EBUOUT2 is digital audio out for professional mode. During reset, the pin is configured as a digital audio output. 16 Table 7. Serial Audio Interface Signals Description Table 8. Digital Audio Interface Signals Description SCF5250 Data Sheet: Technical Data, Rev. 1.3 Freescale Semiconductor ...
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... Table 10 gives the pin descriptions. Flash Memory Signal EBUIN2/SCLKOUT/GPIO13 EBUIN3/CMD_SDIO2/GPIO14 Freescale Semiconductor Table 9. Subcode Interface Signal channel encoder. Subcode sync output This signal is driven high if a subcode sync needs to be inserted in the EFM stream. Subcode data output This signal is a subcode data out pin. ...
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... Secure Digital serial data bit 3 11. Multiplexed signal IIC interface clock or QSPI clock output Function select is done via PLLCR register. PLLCR register. QSPI data output. 4 different QSPI chip selects. SCF5250 Data Sheet: Technical Data, Description Description Rev. 1.3 Freescale Semiconductor ...
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... The processor status pins, PST0/GPIO50, PST1/GPIO49, PST2/INTMON/GPIO48, and PST3/INTMON/GPIO47, indicate the SCF5250 processor status. During debug mode, the timing is synchronous with the processor clock (PSTCLK) and the status is not related to the current bus transfer. Table 12 shows the encodings of these signals. Freescale Semiconductor NOTE SCF5250 Data Sheet: Technical Data, Rev ...
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... Begin 1-byte data transfer on DDATA Begin 2-byte data transfer on DDATA Begin 3-byte data transfer on DDATA Begin 4-byte data transfer on DDATA 2 Exception processing Emulator mode entry exception processing Processor is stopped, waiting for interrupt 2 Processor is halted SCF5250 Data Sheet: Technical Data Rev. 1.3 Freescale Semiconductor ...
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... Recommended Operating Supply Voltages Linear Regulator Operating Specification DC Electrical Specifications Operating Parameters for ADC DC Electrical Characteristics Freescale Semiconductor For See Table 14 on page 22 Table 15 on page 22 Table 16 on page 22 Table 17 on page 23 Table 18 on page 23 Table 19 on page 24 SCF5250 Data Sheet: ...
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... SCF5250 Data Sheet: Technical Data, Value Units -0.5 to +2.5 V +1.32 V +1.08 V -0.5 to +4.6 V +3.6 V +3.0 V -0 -65 to150 C Value Units ο -40 C ° C. Max 1.32V – 3.6V – 3.6V – 3.6V – 1.32V – 1.32V – 3.6V Rev. 1.3 Freescale Semiconductor ...
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... Load Capacitance (BCLKE, SDCAS, SDRAS, SDLDQM, SD_CS0, SDUDQM, SDWE, BUFENB[2:1]) Load Capacitance (SDA0, SDA1, SCL0, SCL1, CMD_SDIO2, SDATA2_BS2, SDATA1_BS1, SDATA0_SDIO1, CS0/CS4, CS1, OE, R/W, TA, TXD[1:0], XTRIM, TDO/DSO, RCK, SFSY, SUBR, SDATA3, TOUT0, QSPID_OUT, QSPICS[3:0], GP[6:5]) Freescale Semiconductor 1 Operating Specification Symbol Vin Vout ...
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... V – offset V 0.73 hyst ADINx Figure 2. Clock Timing Definition SCF5250 Data Sheet: Technical Data, Symbol Min Max C – Typ Max Units – 3.6 V – ADVDD–1.1 v – ADVDD–1 – mV 0.78 0.85 mV – ADVDD–1.1 V Rev. 1.3 Freescale Semiconductor Units pF ...
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... BCLK duty cycle 1 There are only three choices for the valid Audio frequencies 11.29 MHz, 16.93 MHz, or 33.86 MHz; no other values are allowed. The System Clock is derived from one of these crystals via an internal PLL. Freescale Semiconductor NOTE Figure 2 are in relation to the clock. No relationship Table 20 ...
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... Figure 3 and Figure 4 provide the input and output AC timing definition diagrams and Table 22 provide the input and output AC timing parameters. 26 Figure 3. Input/Output Timing Definition-I SCF5250 Data Sheet: Technical Data, Table 21 and Rev. 1.3 Freescale Semiconductor ...
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... BCLK (8mA) Rising to signal Invalid (hold) 3 B10 BCLK (4mA) Rising to signal Valid 3 B11 BCLK (4mA) Rising to signal Invalid (hold) 4 B12 BCLK to High Impedance (Three-State) Freescale Semiconductor B3 B13 H1 Table 21. Input AC Timing Specification Characteristic Table 22. Output AC Timing Specification 1 Characteristic SCF5250 Data Sheet: Technical ...
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... DSCLK and DSI are internally synchronized. This setup time must be met only if recognition on a particular clock is required Characteristic Table 23. Debug AC Timing Specification Characteristic SCF5250 Data Sheet: Technical Data, Min Max Units – tbd ns – tbd Min Max Units – 1.8 – – – ns Rev. 1.3 Freescale Semiconductor ...
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... Num T1 TIN Cycle time T2 TIN Valid to BCLK (input setup) T3 BCLK to TIN Invalid (input hold) T4 BCLK to TOUT Valid (output valid) T5 BCLK to TOUT Invalid (output hold) T6 TIN Pulse Width T7 TOUT Pulse Width Freescale Semiconductor Characteristic SCF5250 Data Sheet: Technical Data Min Max Units 3T – ...
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... BCLK to TXD Invalid (output hold) U7 BCLK to RTS Valid (output valid) U8 BCLK to RTS Invalid (output hold) 30 BCLK U1 RXD U3 CTS U5 TXD U7 RTS Characteristic SCF5250 Data Sheet: Technical Data Min Max Units 6 – – – – ns – tbd ns 3 – ns – tbd ns 3 – ns Rev. 1.3 Freescale Semiconductor ...
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... Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 20 pF load. Freescale Semiconductor Characteristic Characteristic = 0 ...
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... SDA are actively being driven or held low by the processor. 32 M10 BCLK M11 M12 Table 28. I2C Output Bus Timings Characteristic SCF5250 Data Sheet: Technical Data, Table 28 provides the I2C-bus output M13 96 MHz Units Min Max 2 – 4.5 – – – Rev. 1.3 Freescale Semiconductor ...
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... Figure 10. General-Purpose I/O Port AC Timing Definition Diagram Table 29. General-Purpose I/O Port AC Timing Specifications Num P1 GPIO Valid to BCLK (input setup) P2 BCLK to GPIO Invalid (input hold) P3 BCLK to GPIO Valid (output valid) P4 BCLK to GPIO Invalid (output hold) Freescale Semiconductor BCLK Characteristic SCF5250 Data Sheet: Technical Data, Table 29 provides the timing ...
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... Table 30. JTAG AC Timing Specifications Characteristic =0 =2 SCF5250 Data Sheet: Technical Data, Table 30 provides the timing parameters. J3A J3B J8 J10 J12 Min Max 0 10 100 – 25 – 25 – – 5 – – 10 – tbd – tbd – 12 – – 15 – 15 Rev. 1.3 Freescale Semiconductor Units MHz ...
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... SCLK (OUTPUT) SDATAO1, 2 (OUTPUT) Figure 13. SCLK Output, SDATA Output Timing Diagram Table 32. SCLK Output, SDATA Output Timing Specifications Num TU TD Freescale Semiconductor Characteristic TU Characteristic TU Characteristic SCLK fall to SDATAO rise SCLK fall to SDATAO fall SCF5250 Data Sheet: Technical ...
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... Table 36 on page 45 Figure 18 on page 52 Package drawings Figure 19 on page 53 Ball map Figure 20 on page 54 Table 35 SCF5250 Data Sheet: Technical Data, Table 33 provides the timing TH Min Max Units -5 – – ns See provides the pin assignments for the Rev. 1.3 Freescale Semiconductor ...
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... PAD-GND CS0/CS4 Freescale Semiconductor Table 35. 144 QFP Pin Assignments Type Description I/O Data I/O SDRAM address / static adr – – O SDRAM address / static adr O SDRAM address / static adr O SDRAM address / static adr O SDRAM address / static adr O SDRAM address / static adr – ...
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... Out Out / HIGH In / LOW Out / HIGH Out / HIGH Out / HIGH In (requires pull-up for normal operation) In (requires pull-up for normal operation LOW In / LOW – LOW Out / LOW Out / clock out Out / HIGH Out / LOW Out / LOW Out / LOW Rev. 1.3 Freescale Semiconductor ...
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... AUDIO_CLOCK 81 SCLK3/GPIO35 82 SCL0/SDATA1_BS1/ GPIO41 83 SDA0/SDATA3/GPIO42 84 DDATA0/CTS1/ SDATA0_SDIO1/GPIO1 85 DDATA1/RTS1/ SDATA2_BS2/GPIO2 Freescale Semiconductor Type Description I/O QSPI Chip select 1 output / audio interface EBU output 2 I/O QSPI chip select 0 / audio interface EBUIN 4 – – I/O Audio interfaces serial clock 1 I/O Audio interfaces word clock 1 ...
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... Out / HIGH Out / HIGH Out / LOW – – Hi-Z – Out / HIGH In / LOW Out / HIGH Out / HIGH – Out / HIGH Out / HIGH Out / clock output BDM BDM BDM BDM BDM LOW In /LOW Out / LOW Out / clock output X X Rev. 1.3 Freescale Semiconductor ...
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... DATA24 137 DATA23 138 DATA22 139 DATA21 140 DATA20 141 PAD GND 142 DATA19 143 DATA18 144 DATA17 Freescale Semiconductor Type Description I Test I Test I/O SDRAM write enable I/O SDRAM CAS – – I/O SDRAM RAS I/O SDRAM chip select out 0 ...
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... QFP Package The SCF5250 is available in a 144-pin QFP package. For the 144 QFP package drawings, refer to Figure 15 on page 42, Figure 16 on page 43, and Figure 17 on page 44. 42 Figure 15. 144 QFP Package ( SCF5250 Data Sheet: Technical Data, Rev. 1.3 Freescale Semiconductor ...
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... Freescale Semiconductor Figure 16. 144 QFP Package ( SCF5250 Data Sheet: Technical Data, Rev. 1.3 43 ...
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... Figure 17. 144 QFP Package ( SCF5250 Data Sheet: Technical Data, Rev. 1.3 Freescale Semiconductor ...
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... G2 A12 G1 A11 CORE_VDD CORE_VDD C_GND CORE_VSS H2 A10 Freescale Semiconductor Table 36. 196 MAPBGA Pin Assignments Type Description I/O Data I/O SDRAM address / static adr PST_VDD O SDRAM address / static adr O SDRAM address / static adr I/O SDRAM address / static adr O SDRAM address / static adr ...
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... I/O Transfer acknowledge SCF5250 Data Sheet: Technical Data, Pin State After Reset Out Out Out Out Out Out Out Out X X Out Out / High Out / Low Out / High Out / High Out / High In (requires pull-up for normal operation) Rev. 1.3 Freescale Semiconductor ...
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... P9 SCLK1_GP20 M9 LRCK1_GP19 N9 SDATAO1_TOUT1_GP18 P10 SDATAI1_GP17 N10 CFLG_GP5 M10 EF_GP6 P11 QSPICS2_MCLK2_GP24 N11 SDATAI3_GP8 Freescale Semiconductor Type I/O Wake-up input I/O Audio interfaces EBUIN2 / 3 FlashMedia Clock I/O Audio interfaces EBUIN3 / FlashMedia Clock I/O PAD_VDD I/O Audio interfaces EBUIN1 I/O Audio interfaces EBUOUT1 ...
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... UART1 transmit data output SCF5250 Data Sheet: Technical Data, Pin State After Reset In only In only In only In only In only In only In Out / clock output Low Hi-Z Out / High Out / High Out / High Out / High Out / Low Hi-Z Out / High Rev. 1.3 Freescale Semiconductor ...
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... P_GND LIN_GND C10 SDATAO2_GP34 A12 MCLK1_GP11 --- VBGT B11 HIZ_B B10 TEST2 C9 TEST1 A11 TEST0 Freescale Semiconductor Type Description I/O UART1 receive data input I/O Debug / interrupt monitor output 1 I/O Debug / interrupt monitor output 2 I/O PAD_GND I/O Debug I/O Debug I/O Debug ...
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... I/O Data I/O PAD_GND I/O Data I/O Data I/O Data SCF5250 Data Sheet: Technical Data, Pin State After Reset Out / High Out / High Out / High Out / High Out / High Out / High Out / High Out / High Out / High Rev. 1.3 Freescale Semiconductor ...
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... MAPBGA Package and Ball Map The SCF5250 is available in a 196-pin MAPBGA package. For the 196 MAPBGA package drawings, refer to Figure 18 on page 52 and Figure 19 on page 53. For the 196 MAPBGA ball map, refer to Figure 20 on page 54. Freescale Semiconductor Type Description NC ...
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... Figure 18. 196 MAPBGA Package ( SCF5250 Data Sheet: Technical Data, Rev. 1.3 Freescale Semiconductor ...
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... Freescale Semiconductor Figure 19. 196 MAPBGA Package ( SCF5250 Data Sheet: Technical Data, Rev. 1.3 53 ...
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... Figure 20. 196 MAPBGA Ball Map SCF5250 Data Sheet: Technical Data, Rev. 1.3 Freescale Semiconductor ...
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... Added 144 LQFP package drawings. Added 196 MAPBGA package drawings, pin assignments, and ball map. 1.2 Added SCF5250DAG120 and SCF5250EAG120 parts in Content has been reorganized, however there are no other content removal or additions. Freescale Semiconductor Table 37. Revision History Description SCF5250 Data Sheet: Technical Data, Table 1 ...
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... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...