SCF5250LAG100 Freescale Semiconductor, SCF5250LAG100 Datasheet - Page 11

• Manufacturer Part Number: SCF5250LAG100
• Description: IC MPU COLDFIRE 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: SCF52xxr

Specifications of SCF5250LAG100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, I²C, IDE, MMC, SPI, UART/USART
• Peripherals: DMA, I²S, POR, Serial Audio, WDT
• Number Of I /o: 57
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 144-LQFP
• Eeprom Size: -
• Program Memory Size: -

Memory Stick/
Secure Digital interface
ADC IN
ADC OUT
QSPI clock
QSPI data in
QSPI data out
QSPI chip selects
Crystal in
Crystal out
Reset In
Freescale Test Mode
Linear regulator output
Linear regulator input
Linear regulator ground
High Impedance
Debug Data
Freescale Semiconductor
Signal Name
EBUIN3/CMD_SDIO2/GPIO14
EBUIN2/SCLK_OUT/GPIO13
DDATA0/CTS1/SDATA0_SDIO1/GPIO1 Secure Digital serial data bit 0
SCL0/SDATA1_BS1/GPIO41
DDATA1/RTS1/SDATA2_BS2/GPIO2
SDA0/SDATA3/GPIO42
ADIN0/GPI52
ADIN1/GPI53
ADIN2/GPI54
ADIN3/GPI55
ADIN4/GPI56
ADIN5/GPI57
ADREF
ADOUT/SCLK4/GPIO58
QSPI_CLK/SUBR/GPIO25
RCK/QSPI_DIN/QSPI_DOUT/GPIO26 QSPI data input
RCK/QSPI_DIN/QSPI_DOUT/GPIO26
QSPI_DOUT/SFSY/GPIO27
QSPI_CS0/EBUIN4/GPIO15
QSPI_CS1/EBUOUT2/GPIO16
QSPI_CS2/MCLK2/GPIO24
CS1/QSPI_CS3/GPIO28
CRIN
CROUT
RSTI
TEST[2:0]
LINOUT
LININ
LINGND
HI-Z
DDATA0/CTS1/SDATA0_SDIO1/GPIO1
DDATA1/RTS1/SDATA2_BS2/GPIO2
DDATA2/CTS0/GPIO3
DDATA3/RTS0/GPIO4
Table 2. SCF5250 Signal Index (continued)
SCF5250 Data Sheet:
Mnemonic
Technical
Secure Digital command lane
Memory Stick interface 2 data I/O
Clock out for both Memory Stick
interfaces and for Secure Digital
Memory Stick interface 1 data I/O
Secure Digital serial data bit 1
Memory Stick interface 1 strobe
Secure Digital serial data bit 2
Memory Stick interface 2 strobe
Reset output signal
Secure Digital serial data bit 3
Analog to Digital converter input signals
Analog to digital convertor output signal.
Connect to ADREF via integrator
network.
QSPI clock signal
QSPI data out
QSPI chip selects
Crystal input
Crystal Out
Processor Reset Input
TEST pins.
outputs 1.2 V to supply core
Input, typically I/O supply (3.3V)
Assertion Tri-states all output signal pins.
Displays captured processor data and
break-point status.
Data,
Rev. 1.3
Function
–
Output
Input/
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
Out
Out
In
In
In
In
In
In
–
Reset
State
Hi-Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
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