SCF5250LAG100 Freescale Semiconductor, SCF5250LAG100 Datasheet - Page 20

• Manufacturer Part Number: SCF5250LAG100
• Description: IC MPU COLDFIRE 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: SCF52xxr

Specifications of SCF5250LAG100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, I²C, IDE, MMC, SPI, UART/USART
• Peripherals: DMA, I²S, POR, Serial Audio, WDT
• Number Of I /o: 57
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 144-LQFP
• Eeprom Size: -
• Program Memory Size: -

3.19
The SCF5250 complies with the IEEE 1149.1A JTAG testing standard. The JTAG test pins are multiplexed
with background debug pins.
3.20
The clock and reset signals configure the SCF5250 processor and provide interface signals to the external
system.
3.20.1
Asserting RSTI causes the SCF5250SCF5250 to enter reset exception processing. When RSTI is
recognized, the data bus is tri-stated.
20
.
BDM/JTAG Signals
Clock and Reset Signals
1
2
Reset In
Rev. B enhancement.
These encodings are asserted for multiple cycles.
(HEX)
$A
$B
$C
$D
$E
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$F
PST[3:0]
(BINARY)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 12. Processor Status Signal Encodings
SCF5250 Data Sheet:
Continue execution
Begin execution of an instruction
Reserved
Entry into user-mode
Begin execution of PULSE and WDDATA instructions
Begin execution of taken branch or Synch_PC
Reserved
Begin execution of RTE instruction
Begin 1-byte data transfer on DDATA
Begin 2-byte data transfer on DDATA
Begin 3-byte data transfer on DDATA
Begin 4-byte data transfer on DDATA
Exception processing
Emulator mode entry exception processing
Processor is stopped, waiting for interrupt
Processor is halted
Technical
2
2
Definition
Data,
Rev. 1.3
2
2
1
Freescale Semiconductor