HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet
HD64F3664FPV
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HD64F3664FPV Summary of contents
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REJ09B0142-0500Z The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 Rev.5.00 Revision Date: Mar. 18, ...
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Rev. 5.00, 03/04, page ii of xxviii ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The H8/3664 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible ...
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When the E10T is used, NMI is an input/output pin (open-drain in output mode), P85 and P87 are input pins, and P86 is an output pin. Related Manuals: The latest versions of all related manuals are available from our ...
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Rev. 5.00, 03/04, page viii of xxviii ...
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Section 1 Overview............................................................................................1 1.1 Features............................................................................................................................. 1 1.2 Internal Block Diagram..................................................................................................... 2 1.3 Pin Arrangement ............................................................................................................... 4 1.4 Pin Functions .................................................................................................................... 8 Section 2 CPU....................................................................................................11 2.1 Address Space and Memory Map ..................................................................................... 12 2.2 Register Configuration...................................................................................................... 15 2.2.1 General Registers................................................................................................. 16 ...
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Interrupt Exception Handling ........................................................................................... 54 3.4.1 External Interrupts ............................................................................................... 54 3.4.2 Internal Interrupts ................................................................................................ 55 3.4.3 Interrupt Handling Sequence ............................................................................... 56 3.4.4 Interrupt Response Time...................................................................................... 57 3.5 Usage Notes ...................................................................................................................... 59 3.5.1 Interrupts after Reset............................................................................................ 59 3.5.2 Notes on ...
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Subactive Mode ................................................................................................... 87 6.3 Operating Frequency in Active Mode............................................................................... 87 6.4 Direct Transition ............................................................................................................... 87 6.4.1 Direct Transition from Active Mode to Subactive Mode .................................... 87 6.4.2 Direct Transition from Subactive Mode to Active Mode .................................... 88 6.5 ...
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Port 5................................................................................................................................. 115 9.3.1 Port Mode Register 5 (PMR5) ............................................................................. 116 9.3.2 Port Control Register 5 (PCR5) ........................................................................... 117 9.3.3 Port Data Register 5 (PDR5) ............................................................................... 117 9.3.4 Port Pull-Up Control Register 5 (PUCR5)........................................................... 118 9.3.5 Pin Functions ....................................................................................................... ...
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Usage Notes ...................................................................................................................... 147 Section 12 Timer W ...........................................................................................149 12.1 Features............................................................................................................................. 149 12.2 Input/Output Pins .............................................................................................................. 151 12.3 Register Descriptions ........................................................................................................ 152 12.3.1 Timer Mode Register W (TMRW) ...................................................................... 153 12.3.2 Timer Control Register W (TCRW) .................................................................... 153 12.3.3 ...
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Transmit Data Register (TDR)............................................................................. 184 14.3.5 Serial Mode Register (SMR) ............................................................................... 185 14.3.6 Serial Control Register 3 (SCR3) ........................................................................ 186 14.3.7 Serial Status Register (SSR) ................................................................................ 188 14.3.8 Bit Rate Register (BRR) ...................................................................................... 190 14.4 Operation in Asynchronous Mode ...
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Slave Receive Operation...................................................................................... 241 15.4.5 Slave Transmit Operation .................................................................................... 243 15.4.6 Clock Synchronous Serial Format ....................................................................... 245 15.4.7 IRIC Setting Timing and SCL Control ................................................................ 245 15.4.8 Noise Canceler..................................................................................................... 247 15.4.9 Sample Flowcharts............................................................................................... 247 15.5 Usage Notes ...................................................................................................................... 252 ...
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Noise Suppression Time ...................................................................................... 278 Section 18 Power Supply Circuit ...................................................................... 279 18.1 When Using Internal Power Supply Step-Down Circuit .................................................. 279 18.2 When Not Using Internal Power Supply Step-Down Circuit............................................ 280 Section 19 List of Registers............................................................................... 281 19.1 ...
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Appendix E EEPROM Stacked-Structure Cross-Sectional View .....................379 Main Revisions and Additions in this Edition .....................................................381 Index .........................................................................................................385 Rev. 5.00, 03/04, page xvii of xxviii ...
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Rev. 5.00, 03/04, page xviii of xxviii ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of H8/3664 of F-ZTAT Figure 1.2 Internal Block Diagram of H8/3664N of F-ZTAT Figure 1.3 Pin Arrangement of H8/3664 of F-ZTAT (FP-64E, FP-64A).......................................................................................................... 4 Figure 1.4 Pin Arrangement of H8/3664 of F-ZTAT ...
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Figure 4.5 Operation when the Instruction Set is not Executed and does not Branch due to Conditions not Being Satisfied .................................................................................... 67 Section 5 Clock Pulse Generators Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69 Figure 5.2 Block Diagram ...
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Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 146 Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 147 Figure 11.12 Contention between TCORA Write and Compare Match ..................................... 148 Figure 11.13 Internal Clock Switching and TCNTV Operation ...
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Figure 14.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits) .............. 195 Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 196 Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit ...
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Figure 15.14 Sample Flowchart for Master Receive Mode ........................................................ 249 Figure 15.15 Sample Flowchart for Slave Receive Mode .......................................................... 250 Figure 15.16 Sample Flowchart for Slave Transmit Mode......................................................... 251 Figure 15.17 Flowchart and Timing of Start Condition Instruction Issuance for ...
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Figure B.9 Port 5 Block Diagram (P55) ..................................................................................... 363 Figure B.10 Port 5 Block Diagram (P54 to P50) ........................................................................ 364 Figure B.11 Port 7 Block Diagram (P76) ................................................................................... 365 Figure B.12 Port 7 Block Diagram (P75) ................................................................................... 366 Figure B.13 ...
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Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 8 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 22 Table 2.2 Data Transfer Instructions....................................................................................... 23 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 24 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 25 ...
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Table 7.7 Flash Memory Operating States............................................................................ 104 Section 10 Timer A Table 10.1 Pin Configuration.................................................................................................. 130 Section 11 Timer V Table 11.1 Pin Configuration.................................................................................................. 136 Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 139 Section 12 ...
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Table 20 Bus Interface Timing ...................................................................................... 301 Table 20.5 Serial Interface (SCI3) Timing ............................................................................. 302 Table 20.6 A/D Converter Characteristics .............................................................................. 303 Table 20.7 Watchdog Timer Characteristics........................................................................... 304 Table 20.8 Flash Memory Characteristics .............................................................................. 305 Table 20.9 ...
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Rev. 5.00, 03/04, page xxviii of xxviii ...
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Features • High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions • Various peripheral functions Timer A (can be ...
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Compact package Package Code LQFP-64 FP-64E QFP-64 FP-64A LQFP-48 FP-48F LQFP-48 FP-48B SDIP-42 DP-42S Only LQFP-64 (FP-64E) for H8/3664N package 1.2 Internal Block Diagram System Subclock generator generator P10/TMOW P11 P12 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV P20/SCK3 P21/RXD P22/TXD Figure ...
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System Subclock clock generator generator P10/TMOW P11 P12 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV P20/SCK3 P21/RXD P22/TXD SDA SCL Note : The H8/3664N is a stacked-structure product in which an EEPROM chip is mounted on the TM H8/3664F-ZTAT version. Figure 1.2 Internal ...
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Pin Arrangement P14/IRQ0 52 P15/IRQ1 P16/IRQ2 53 54 P17/IRQ3/TRGV 55 PB4/AN4 56 PB5/AN5 57 PB6/AN6 58 PB7/AN7 59 PB3/AN3 PB2/AN2 60 61 PB1/AN1 62 PB0/AN0 Note: Do not connect NC ...
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P14/IRQ0 37 P15/IRQ1 38 P16/IRQ2 39 P17/IRQ3/TRGV 40 PB4/AN4 41 PB5/AN5 42 PB6/AN6 43 PB7/AN7 44 PB3/AN3 45 PB2/AN2 46 PB1/AN1 47 PB0/AN0 Figure 1.4 ...
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PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 RES TEST V OSC2 OSC1 V P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5/ADTRG P10/TMOW Note: DP-42S has no P11, P12, PB4/AN4, PB5/AN5, PB6/AN6, and PB7/AN7 pins. Figure 1.5 Pin Arrangement of H8/3664 of ...
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P14/IRQ0 52 P15/IRQ1 P16/IRQ2 53 54 P17/IRQ3/TRGV 55 PB4/AN4 56 PB5/AN5 57 PB6/AN6 58 PB7/AN7 59 PB3/AN3 60 PB2/AN2 ...
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Pin Functions Table 1.1 Pin Functions FP-64E, Type Symbol FP-64A Power source pins Clock pins OSC1 11 OSC2 System control RES 7 ...
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FP-64E, Type Symbol FP-64A Timer A TMOW 23 Timer V TMOV 30 TMCIV 29 TMRIV 28 TRGV 54 Timer W FTCI 36 FTIOA FTIOD bus SDA 26* inerface 2 SCL 27* Serial ...
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FP-64E, Type Symbol FP-64A I/O ports P76 P74 P87 P80 Note : 1. These pins are only available for the I 2 the I C bus is disabled after canceling a reset, ...
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This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs ...
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Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map. HD64F3664 (Flash memory version) H'0000 Interrupt vector H'0033 H'0034 On-chip ...
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HD6433662 (Mask ROM version) H'0000 Interrupt vector H'0033 H'0034 On-chip ROM (16 kbytes) H'3FFF Not used H'FD80 On-chip RAM (512 bytes) H'FF7F H'FF80 Internal I/O register H'FFFF HD6433663 (Mask ROM version) H'0000 Interrupt vector H'0033 H'0034 On-chip ROM (24 kbytes) ...
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Rev. 5.00, 03/04, page 14 of 388 HD64N3664 (On-chip EEPROM module) H'0000 User area (512 bytes) H'01FF Not used H'FF09 Slave address register Not used Figure 2.1 Memory Map (3) ...
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Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register ...
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General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it ...
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SP (ER7) Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), ...
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Bit Bit Name Initial Value undefined 5 H undefined 4 U undefined 3 N undefined 2 Z undefined 1 V undefined 0 C undefined Rev. 5.00, 03/04, page 18 of 388 R/W Description R/W Interrupt ...
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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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Data Type General Data Format Register Word data Rn Word data En 15 MSB Longword ERn data 31 MSB Legend ERn : General register General register General register R RnH : General register RH ...
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Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address attempt is made ...
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Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.1 ...
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Table 2.2 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd, ...
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Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L SUB Performs addition or subtraction on data in two general registers immediate data and data in a ...
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Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ...
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Table 2.4 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → ...
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Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the ...
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Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry ...
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Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC ...
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Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR LDC B/W Moves the source operand contents ...
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Table 2.9 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B — else next ≠ 0 then EEPMOV.W — else next; Transfers a data block. Starting from the address set in ER5, transfers data ...
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Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. ...
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Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU ...
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Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum ...
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Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the ...
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Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective ...
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Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Legend r, rm,rn : Register field op : Operation field disp : Displacement IMM : Immediate data abs : Absolute address Effective Address Calculation PC contents ...
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Basic Bus Cycle CPU operation is synchronized by a system clock (ø subclock (ø edge of ø or ø to the next rising edge is called one state. A bus cycle consists of two states or SUB ...
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On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing ...
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CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. In the program halt state there are a sleep mode, ...
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Reset state Reset occurs Program halt state 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to ...
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Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers ...
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Prior to executing BSET P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 BSET instruction executed BSET #0, @PDR5 After executing BSET P57 P56 Input/output Input Input Pin state Low High level ...
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Prior to executing BSET MOV.B #80, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PDR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 1 0 BSET instruction executed BSET #0, @RAM0 After ...
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Prior to executing BCLR P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 BCLR instruction executed BCLR #0, @PCR5 After executing BCLR P57 P56 Input/output Output Output Pin state Low High level ...
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Prior to executing BCLR MOV.B #3F, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PCR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 0 0 BCLR instruction executed BCLR #0, @RAM0 After ...
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Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES ...
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Table 3.1 Exception Sources and Vector Address Relative Module Exception Sources RES pin Reset Watchdog timer Reserved for system use External interrupt NMI pin CPU Trap instruction (#0) Address break Break conditions satisfied CPU Direct transition by executing the ...
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Register Descriptions Interrupts are controlled by the following registers. • Interrupt edge select register 1 (IEGR1) • Interrupt edge select register 2 (IEGR2) • Interrupt enable register 1 (IENR1) • Interrupt flag register 1 (IRR1) • Wakeup interrupt flag ...
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Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Bit Bit Name Initial Value WPEG5 0 ...
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Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, timer A overflow interrupts, and external pin interrupts. Bit Bit Name Initial Value 7 IENDT 0 6 IENTA 0 5 IENWP 0 IEN3 0 2 ...
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Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3 to IRQ0 interrupt requests. Bit Bit Name Initial Value 7 IRRDT 0 6 IRRTA 0 ...
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Wakeup Interrupt Flag Register (IWPR) IWPR is a status flag register for WKP5 to WKP0 interrupt requests. Bit Bit Name Initial Value IWPF5 0 4 IWPF4 0 3 IWPF3 0 2 IWPF2 ...
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Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure ...
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WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending ...
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Interrupt Handling Sequence 3.4.3 Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows interrupt occurs while the NMI or interrupt enable bit is set interrupt request signal is sent to ...
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SP – – – – (R7) Stack area Prior to start of interrupt exception handling Legend Upper 8 bits of program counter (PC Lower 8 bits ...
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Rev. 5.00, 03/04, page 58 of 388 Figure 3.3 Interrupt Sequence ...
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Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, ...
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Rev. 5.00, 03/04, page 60 of 388 ...
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Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can ...
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Address Break Control Register (ABRKCR) ABRKCR sets address break conditions. Bit Bit Name Initial Value 7 RTINTE 1 6 CSEL1 0 5 CSEL0 0 4 ACMP2 0 3 ACMP1 0 2 ACMP0 0 1 DCMP1 0 0 DCMP0 0 ...
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Table 4.1 Access and Data Bus Used ROM space RAM space I/O register with 8-bit data bus width I/O register with 16-bit data bus width 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and ...
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Address Break Control Register (ABRKCR), for details. The initial value of this register is undefined. 4.2 Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the ...
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When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A MOV instruc- tion 1 prefetch φ Address 025C bus Interrupt request Figure 4.2 Address Break Interrupt Operation Example (2) ...
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When another interrupt request is accepted before an instruction to which an address break is set is executed, exception handling of an address break interrupt is not executed. However, the ABIF bit is set to 1 (see figure 4.4). Therefore ...
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ADBRKCR = H'80 • BAR = H'0150 Address bus Address break interrupt request Figure 4.5 Operation when the Instruction Set is not Executed and does not Branch due to [Program] 0134 BNE 0136 NOP 0138 NOP . ...
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Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty ...
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System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator providing external clock input. Figure 5.2 shows a block diagram of the system clock generator. OSC ...
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Table 5.1 Crystal Resonator Parameters Frequency (MHz) 2 500 Ω R (max (max 5.1.2 Connecting Ceramic Resonator Figure 5.5 shows a typical method of connecting a ceramic resonator. Figure 5.5 Typical Connection to Ceramic Resonator ...
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Subclock Generator Figure 5.7 shows a block diagram of the subclock generator. Figure 5.7 Block Diagram of Subclock Generator 5.2.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, ...
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Pin Connection when Not Using Subclock When the subclock is not used, connect pin X figure 5.10. Figure 5.10 Pin Connection when not Using Subclock 5.3 Prescalers 5.3.1 Prescaler S Prescaler 13-bit counter using the system ...
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Suitable constants should be determined in consultation with the resonator element manufacturer. Design the circuit so that the resonator element never receives voltages exceeding its maximum ...
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Notes on Board Design When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC 1 resonator circuit to prevent induction from interfering with correct oscillation (see figure 5.11). ...
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Rev. 5.00, 03/04, page 76 of 388 ...
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Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting ...
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Register Descriptions The registers related to power-down modes are listed below. • System control register 1 (SYSCR1) • System control register 2 (SYSCR2) • Module standby control register 1 (MSTCR1) 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the ...
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Bit Bit Name Initial Value 7 SSBY 0 6 STS2 0 5 STS1 0 4 STS0 0 3 NESEL 0 R/W Description R/W Software Standby This bit selects the mode to ...
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Table 6.1 Operating Frequency and Waiting Time STS2 STS1 STS0 Waiting Time 8,192 states 1 16,384 states 1 0 32,768 states 1 65,536 states 131,072 states 1 1,024 states 1 0 128 states 1 ...
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System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit Bit Name Initial Value 7 SMSEL 0 6 LSON 0 5 DTON 0 4 MA2 0 3 MA1 0 2 MA0 0 1 SA1 ...
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Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value MSTIIC 0 5 MSTS3 0 4 MSTAD 0 3 MSTWD ...
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Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts ...
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Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling DTON SSBY SMSEL Legend Don’t care. * When a state transition is performed while SMSEL is ...
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Table 6.3 Internal State in Each Operating Mode Function Active Mode System clock oscillator Functioning Subclock oscillator Functioning CPU Instructions Functioning operations Registers Functioning RAM Functioning IO ports Functioning External IRQ3 to IRQ0 Functioning interrupts WKP5 to WKP0 Functioning Peripheral ...
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Standby Mode In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, on- chip RAM, and some on-chip ...
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Subactive Mode The operating frequency of subactive mode is selected from ø SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to the frequency which is set before the execution. When the SLEEP instruction ...
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Example Direct transition time = ( × tosc + 14 × 8tw = 3tosc + 112tw (when the CPU operating clock of ø Legend tosc: OSC clock cycle time tw: watch clock cycle time tcyc: system clock (ø) ...
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The features of the 32-kbyte flash memory built into the flash memory version are summarized below. • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is ...
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H'0000 Erase unit H'0080 1kbyte H'0380 H'0400 Erase unit H'0480 1kbyte H'0780 H'0800 Erase unit H'0880 1kbyte H'0B80 H'0C00 Erase unit H'0C80 1kbyte H'0F80 H'1000 Erase unit H'1080 28 kbytes H'7F80 Figure 7.1 Flash Memory Block Configuration 7.2 Register Descriptions ...
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Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing. Bit ...
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Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit Bit Name Initial Value 7 FLER ...
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Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of ...
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When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI3. After erasing the entire flash memory, the programming control ...
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The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. Before branching to the programming control program, the chip terminates transfer operations by SCI3 (by clearing the RE and ...
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Table 7.2 Boot Mode Operation Host Operation Processing Contents Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. Boot program erase error H'AA reception Transmits number of bytes (N) of programming control ...
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Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 16 MHz 9,600 bps MHz 4,800 bps MHz ...
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Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: ...
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Write pulse application subroutine Apply Write Pulse WDT enable Set PSU bit in FLMCR1 * Wait 50 µs Set P bit in FLMCR1 Wait (Wait time=programming time) Clear P bit in FLMCR1 Wait 5 µs Clear PSU bit in FLMCR1 ...
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Table 7.4 Reprogram Data Computation Table Program Data Verify Data Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Table 7.6 Programming Time ...
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If the read data is not erased successfully, set erase mode again, and repeat the erase/erase- verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory All ...
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Increment address Note: *The RTS instruction must not be used during a period between dummy writing of H' verify address and verify data reading. Figure 7.4 Erase/Erase-Verify Flowchart Rev. 5.00, 03/04, page 102 of 388 Erase start SWE ...
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Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because ...
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Programmer Mode In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip 64-kbyte flash ...
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This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification Flash memory version H8/3664N TM ...
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Rev. 5.00, 03/04, page 106 of 388 ...
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The group of this LSI has twenty-nine general I/O ports (twenty-seven ports for H8/3664N) and eight general input-only ports. Port large current port, which can drive 20 mA (@V V) when a low level signal is output. ...
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Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W 7 IRQ3 0 6 IRQ2 0 5 IRQ1 0 4 IRQ0 0 ...
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Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W 7 PCR17 0 6 PCR16 0 5 PCR15 0 4 ...
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Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value 7 PUCR17 0 6 PUCR16 0 5 PUCR15 0 4 PUCR14 0 ...
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P15/IRQ1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Setting value Legend X: Don't care. P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Setting value Legend X: Don't care. ...
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P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Setting value Legend X: Don't care. 9.2 Port 2 Port general I/O port also functioning as a SCI3 I/O pin. Each pin of ...
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Port Control Register 2 (PCR2) PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2. Bit Bit Name Initial Value R/W 7 6 5 ...
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Pin Functions The correspondence between the register specification and the port functions is shown below. P22/TXD pin Register PMR1 PCR2 Bit Name TXD PCR22 Setting Value Legend X: Don't care. P21/RXD pin Register SCR3 ...
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Port 5 Port general I/O port also functioning pin, wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting 2 of the I C bus ...
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Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Bit Bit Name Initial Value R/W Description WKP5 0 4 WKP4 0 3 WKP3 0 2 WKP2 0 ...
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Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit Bit Name Initial Value R/W 7 PCR57 0 6 PCR56 0 5 PCR55 0 4 ...
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Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value PUCR55 0 4 PUCR54 0 ...
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P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Setting Value Legend X: Don't care. P54/WKP4 pin Register PMR5 PCR5 Bit Name WKP4 PCR54 Setting Value Legend X: Don't care. ...
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P51/WKP1 pin Register PMR5 PCR5 Bit Name WKP1 PCR51 Setting Value Legend X: Don't care. P50/WKP0 pin Register PMR5 PCR5 Bit Name WKP0 PCR50 Setting Value Legend X: Don't care. ...
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Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Bit Bit Name Initial Value R/W PCR76 0 5 PCR75 0 4 ...
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Pin Functions The correspondence between the register specification and the port functions is shown below. P76/TMOV pin Register TCSRV PCR7 Bit Name OS3 to OS0 PCR76 Setting Value 0000 0 1 Other than X the above values Legend X: ...
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Port 8 Port general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. The register setting of the timer W has priority for functions ...
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Port Data Register 8 (PDR8) PDR8 is a general I/O port data register of port 8. Bit Bit Name Initial Value R/W 7 P87 0 6 P86 0 5 P85 0 4 P84 0 3 P83 0 2 P82 ...
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P84/FTIOD pin Register TIOR1 Bit Name IOD2 IOD1 Setting Value Legend X: Don't care. P83/FTIOC pin Register TIOR1 Bit Name IOC2 IOC1 Setting Value ...
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P81/FTIOA pin Register TIOR0 Bit Name IOA2 IOA1 Setting Value Legend X: Don't care. P80/FTCI pin Register PCR8 Bit Name PCR80 Pin Function Setting Value 0 P80 input/FTCI input pin 1 P80 ...
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Port Data Register B (PDRB) PDRB is a general input-only port data register of port B. Bit Bit Name Initial Value R/W 7 PB7 6 PB6 5 PB5 4 PB4 3 PB3 2 ...
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Rev. 5.00, 03/04, page 128 of 388 ...
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Timer 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 10.1 shows a block diagram of timer A. 10.1 Features • Timer ...
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W ø ø /32 W ø /16 W ø ø TMOW ø /32 W ø /16 W ø ø ø Legend TMA: Timer mode register A TCA: Timer ...
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Timer Mode Register A (TMA) TMA selects the operating mode, the divided clock output, and the input clock. Bit Bit Name Initial Value R/W 7 TMA7 0 6 TMA6 0 5 TMA5 0 TMA3 0 ...
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Bit Bit Name Initial Value R/W 2 TMA2 0 1 TMA1 0 0 TMA0 0 Legend X: Don't care. 10.3.2 Timer Counter A (TCA) TCA is an 8-bit readable up-counter, which is incremented by internal clock input. The clock source ...
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CPU interrupt is requested. At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as an interval timer that generates an overflow output at intervals of 256 input ...
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Rev. 5.00, 03/04, page 134 of 388 ...
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Timer 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an ...
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TRGV Clock select TMCIV ø PSS TMRIV TMOV Legend: TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0 TCRV1: Timer control register V1 PSS: Prescaler ...
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Register Descriptions Time V has the following registers. • Timer counter V (TCNTV) • Timer constant register A (TCORA) • Timer constant register B (TCORB) • Timer control register V0 (TCRV0) • Timer control/status register V (TCSRV) • Timer ...
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Timer Control Register V0 (TCRV0) TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request. Bit Bit Name Initial Value R/W 7 CMIEB 0 6 CMIEA 0 5 OVIE 0 ...
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Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions TCRV0 Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 TCRV1 Bit 0 ICKS0 Description ...
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Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Bit Bit Name Initial Value R/W 7 CMFB 0 6 CMFA 0 5 OVF 0 OS3 0 ...
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OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the ...
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Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figure ...
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TMCIV (External clock input pin) TCNTV input clock N – 1 TCNTV Figure 11.3 Increment Timing with External Clock ø TCNTV H'FF Overflow signal OVF Figure 11.4 OVF Set Timing ø TCNTV N TCORA or N TCORB Compare match ...
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Compare match A signal Timer V output pin ø Compare match A signal TCNTV Figure 11.7 Clear Timing by Compare Match ø TMRIV(External counter reset input pin ) TCNTV reset signal TCNTV Figure 11.8 Clear Timing by TMRIV Input ...
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Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared ...
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Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. ...
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Usage Notes The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle TCNTV clear signal is generated in the ...
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Address Internal write signal TCNTV TCORA Compare match signal Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV Figure 11.13 Internal Clock Switching and TCNTV Operation Rev. 5.00, 03/04, page 148 ...
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The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. ...
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Table 12.1 Timer W Functions Item Counter Internal clocks: φ, φ/2, φ/4, φ/8 Count clock External clock: FTCI General registers Period (output compare/input specified in capture registers) GRA Counter clearing function GRA compare match Initial output value — setting function ...
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Internal clock: ø ø/2 ø/4 ø/8 External clock: FTCI Comparator Legend: TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer status register W (8 bits) ...
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Register Descriptions The timer W has the following registers. • Timer mode register W (TMRW) • Timer control register W (TCRW) • Timer interrupt enable register W (TIERW) • Timer status register W (TSRW) • Timer I/O control register ...
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Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Bit Bit Name Initial Value R/W 7 CTS 0 BUFEB 0 4 BUFEA 0 PWMD ...
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Bit Bit Name Initial Value 7 CCLR 0 6 CKS2 0 5 CKS1 0 4 CKS0 0 3 TOD 0 2 TOC 0 1 TOB 0 0 TOA 0 Legend X: Don't care. Note: * The change of the setting ...
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Timer Interrupt Enable Register W (TIERW) TIERW controls the timer W interrupt request. Bit Bit Name Initial Value R/W 7 OVIE 0 IMIED 0 2 IMIEC 0 1 IMIEB ...
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Bit Bit Name Initial Value 3 IMFD 0 2 IMFC 0 1 IMFB 0 0 IMFA 0 Rev. 5.00, 03/04, page 156 of 388 R/W Description R/W Input Capture/Compare Match Flag D [Setting conditions] • TCNT = GRD when GRD ...
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Timer I/O Control Register 0 (TIOR0) TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Bit Bit Name Initial Value R/W IOB2 0 5 IOB1 0 ...
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Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Bit Bit Name Initial Value IOD2 0 5 IOD1 0 4 ...
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Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR in TCRW ...
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Operation The timer W has the following operating modes. • Normal Operation • PWM Operation 12.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a free- running counter. When the CTS ...
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TCNT value GRA H'0000 CTS bit IMFA Figure 12.3 Periodic Counter Operation By setting a general register as an output compare register, compare match can cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD ...
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TCNT value H'FFFF GRA GRB H'0000 FTIOA FTIOB Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 12.6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by compare match A. Toggle ...
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TCNT value H'FFFF H'F000 H'AA55 H'55AA H'1000 H'0000 FTIOA GRA H'1000 FTIOB GRB Figure 12.7 Input Capture Operating Example Figure 12.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set ...
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PWM Operation In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins three-phase PWM ...
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TCNT value GRA GRB GRC GRD H'0000 FTIOB FTIOC FTIOD Figure 12.10 PWM Mode Example (2) Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer ...
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TCNT value Write to GRB GRA GRB H'0000 FTIOB TCNT value Write to GRB GRA GRB H'0000 FTIOB TCNT value Write to GRB GRA GRB H'0000 FTIOB (TOB, TOC, and TOD = 0: initial output values are set to 0) ...
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TCNT value Write to GRB GRA GRB H'0000 FTIOB TCNT value Write to GRB GRA GRB H'0000 FTIOB TCNT value Write to GRB GRA GRB H'0000 FTIOB Figure 12.13 PWM Mode Example (TOB, TOC, and TOD = 1: initial output ...
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Operation Timing 12.5.1 TCNT Count Timing Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure 12.15 shows the timing when the external clock source is selected. The pulse width of the external clock ...
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Figure 12.16 shows the output compare timing. φ TCNT input clock TCNT GRA to GRD Compare match signal FTIOA to FTIOD Figure 12.16 Output Compare Output Timing 12.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or ...
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Timing of Counter Clearing by Compare Match Figure 12.18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from and its cycle is N ...
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Input capture signal TCNT GRA, GRB GRC, GRD Figure 12.20 Buffer Operation Timing (Input Capture) 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an ...
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Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an ...