C8051F120-GQ Silicon Laboratories Inc, C8051F120-GQ Datasheet - Page 178
![IC 8051 MCU FLASH 128K 100TQFP](/photos/12/21/122164/c8051f120-gq_sml.jpg)
C8051F120-GQ
Manufacturer Part Number
C8051F120-GQ
Description
IC 8051 MCU FLASH 128K 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F120-GQ
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
8448Byte
Cpu Speed
100MHz
No. Of Timers
5
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1223
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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
13.1. Power-on Reset
The C8051F120/1/2/3/4/5/6/7 family incorporates a power supply monitor that holds the MCU in the reset
state until V
to Table 13.1 for the Electrical Characteristics of the power supply monitor circuit. The RST pin is asserted
low until the end of the 100 ms V
Monitor reset is enabled and disabled using the external V
Monitor is enabled, it is selected as a reset source using the PORSF bit. If the RSTSRC register is written
by firmware, PORSF (RSTSRC.1) must be written to ‘1’ for the V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other
reset flags in the RSTSRC Register are indeterminate. PORSF is cleared by all other resets. Since all
resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag
to determine if a power-up was the cause of reset. The contents of internal data memory should be
assumed to be undefined after a power-on reset.
13.2. Power-fail Reset
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and return the CIP-51 to the reset state. When V
above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on reset (see
Figure 13.2). Note that even though internal data memory contents are not altered by the power-fail reset,
it is impossible to determine if V
set to logic 1, the data may no longer be valid.
178
Logic HIGH
Logic LOW
DD
rises above the V
2.70
2.55
2.0
1.0
/RST
V
RST
DD
RST
DD
dropped below the level required for data retention. If the PORSF flag is
Monitor timeout in order to allow the V
Figure 13.2. Reset Timing
level during power-up. See Figure 13.2 for timing diagram, and refer
Power-On Reset
100ms
Rev. 1.4
DD
monitor enable pin (MONEN). When the V
DD
DD
to drop below V
Monitor to be effective.
VDD Monitor Reset
DD
supply to stabilize. The V
100ms
RST
DD
, the power supply
returns to a level
t
DD
DD
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