C8051F120-GQ Silicon Laboratories Inc, C8051F120-GQ Datasheet - Page 91
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C8051F120-GQ
Manufacturer Part Number
C8051F120-GQ
Description
IC 8051 MCU FLASH 128K 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F120-GQ
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
8448Byte
Cpu Speed
100MHz
No. Of Timers
5
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1223
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F120-GQ
Manufacturer:
SiliconL
Quantity:
4 353
Company:
Part Number:
C8051F120-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F120-GQR
Manufacturer:
PEAK
Quantity:
5 000
Company:
Part Number:
C8051F120-GQR
Manufacturer:
SILICON
Quantity:
2
Company:
Part Number:
C8051F120-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F120-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
7.
The C8051F12x devices include a second ADC peripheral (ADC2), which consists of an 8-channel, config-
urable analog multiplexer, a programmable gain amplifier, and a 500 ksps, 8-bit successive-approximation-
register ADC with integrated track-and-hold (see block diagram in Figure 7.1). ADC2 is fully configurable
under software control via the Special Function Registers shown in Figure 7.1. The ADC2 subsystem (8-bit
ADC, track-and-hold and PGA) is enabled only when the AD2EN bit in the ADC2 Control register
(ADC2CN) is set to logic 1. The ADC2 subsystem is in low power shutdown when this bit is logic 0. The
voltage reference used by ADC2 is selected as described in
page 113
7.1.
Eight ADC2 channels are available for measurement, as selected by the AMX2SL register (see SFR Defi-
nition 7.2). The PGA amplifies the ADC2 output signal by an amount determined by the states of the
AMP2GN2-0 bits in the ADC2 Configuration register, ADC2CF (SFR Definition 7.3). The PGA can be soft-
ware-programmed for gains of 0.5, 1, 2, or 4. Gain defaults to 0.5 on reset.
Important Note : AIN2 pins also function as Port 1 I/O pins, and must be configured as analog inputs when
used as ADC2 inputs. To configure an AIN2 pin for analog input, set to ‘0’ the corresponding bit in register
P1MDIN. Port 1 pins selected as analog inputs are skipped by the Digital I/O Crossbar. See
“18.1.5. Configuring Port 1 Pins as Analog Inputs” on page 240
the AIN2 pins.
AIN2.0 (P1.0)
AIN2.1 (P1.1)
AIN2.2 (P1.2)
AIN2.3 (P1.3)
AIN2.4 (P1.4)
AIN2.5 (P1.5)
AIN2.6 (P1.6)
AIN2.7 (P1.7)
ADC2 (8-Bit ADC, C8051F12x Only)
Analog Multiplexer and PGA
.
AMX2CF
Figure 7.1. ADC2 Functional Block Diagram
+
+
+
+
-
-
-
-
AMUX
8-to-1
AMX2SL
X
+
-
AV+
AD2EN
ADC2GTH
AGND
Rev. 1.4
ADC2CF
C8051F120/1/2/3/4/5/6/7
ADC
8-Bit
SAR
AV+
ADC2CN
ADC2LTH
Section “9. Voltage Reference” on
for more information on configuring
C8051F130/1/2/3
Start Conversion
8
8
000
001
010
011
1xx
8
16
Write to AD2BUSY
Timer 3 Overflow
CNVSTR2
Timer 2 Overflow
Write to AD0BUSY
(synchronized with
ADC0)
Comp
Dig
AD2WINT
Section
91