C8051F120-GQ Silicon Laboratories Inc, C8051F120-GQ Datasheet - Page 36
![IC 8051 MCU FLASH 128K 100TQFP](/photos/12/21/122164/c8051f120-gq_sml.jpg)
C8051F120-GQ
Manufacturer Part Number
C8051F120-GQ
Description
IC 8051 MCU FLASH 128K 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F120-GQ
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
8448Byte
Cpu Speed
100MHz
No. Of Timers
5
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1285 - KIT DEV EMBEDDED MODEM336-1284 - KIT DEV EMBEDDED ETHERNET336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1223
Available stocks
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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
1.10. 12-bit Digital to Analog Converters
The C8051F12x devices have two integrated 12-bit Digital to Analog Converters (DACs). The MCU data
and control interface to each DAC is via the Special Function Registers. The MCU can place either or both
of the DACs in a low power shutdown mode.
The DACs are voltage output mode and include a flexible output scheduling mechanism. This scheduling
mechanism allows DAC output updates to be forced by a software write or scheduled on a Timer 2, 3, or 4
overflow. The DAC voltage reference is supplied from the dedicated VREFD input pin on the 100-pin TQFP
devices or via the internal Voltage reference on the 64-pin TQFP devices. The DACs are especially useful
as references for the comparators or offsets for the differential inputs of the ADCs.
36
DAC0MD1
DAC0MD0
DAC1MD1
DAC1MD0
DAC0DF2
DAC0DF1
DAC0DF0
DAC1DF2
DAC1DF1
DAC1DF0
DAC0EN
DAC1EN
8
8
8
8
Figure 1.15. DAC System Block Diagram
8
8
8
8
12
12
REF
REF
Rev. 1.4
DAC0
DAC1
AGND
AGND
AV+
AV+
DAC0
DAC1
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