MC56F8355VFGE Freescale Semiconductor, MC56F8355VFGE Datasheet - Page 20

• Manufacturer Part Number: MC56F8355VFGE
• Description: IC DSP 16BIT 60MHZ 128-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8355VFGE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 49
• Program Memory Size: 264KB (132K x 16)
• Program Memory Type: FLASH
• Ram Size: 10K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 128-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 49
• Data Ram Size: 20 KB
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, CAN
• Minimum Operating Temperature: - 40 C
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20
Signal Name
CLKMODE
V
OCR_DIS
EXTAL
SSA_ADC
V
V
V
V
XTAL
V
V
CAP
CAP
CAP
CAP
PP
PP
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
1
2
1
2
3
4
Pin No.
122
119
95
71
49
75
13
79
74
73
5
Supply
Supply
Output
Input/
Type
Input
Input
Input
Input
Chip-driven
During
56F8355 Technical Data, Rev. 17
Supply
Reset
State
Input
Input
Input
Input
ADC Analog Ground — This pin supplies an analog ground to
the ADC modules.
On-Chip Regulator Disable —
Tie this pin to V
Tie this pin to V
This pin is intended to be a static DC signal from power-up to
shut down. Do no try to toggle this pin for power savings
during operation.
V
connect each pin to a 2.2 F or greater bypass capacitor in order
to bypass the core logic voltage regulator, required for proper chip
operation. When OCR_DIS is tied to V
these pins become V
regulated 2.5V power supply.
Note: This bypass is required even if the chip is powered with
an external supply.
V
circuit for normal functionality.
Clock Input Mode Selection — This input determines the
function of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive the input
clock of the chip. The EXTAL pin should be grounded.
0 = A crystal or ceramic resonator should be connected between
XTAL and EXTAL.
External Crystal Oscillator Input — This input can be connected
to an 8MHz external crystal. Tie this pin low if XTAL is driven by
an external clock source.
Crystal Oscillator Output — This output connects the internal
crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to GND.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for
the on-chip PLL.
CAP
PP
1 - V
1 - 4 — When OCR_DIS is tied to V
PP
2 — These pins should be left unconnected as an open
SS
DD
to enable the on-chip regulator.
to disable the on-chip regulator.
DD_CORE
Signal Description
and should be connected to a
DD
SS
(regulator disabled),
Freescale Semiconductor
(regulator enabled),
Preliminary