MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 173
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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6.2.8.3
The WCR,
any value to WCR resets the counter and prescaler and should be executed on a regular basis if the
watchdog is enabled.
6.2.8.4
The WER,
Table 6-11
Freescale Semiconductor
15-1
15–1
Bits
Bits
0
0
Address
Address
Field
REF
Field
IEN
Reset
Reset
WIE
Field
Field
—
R/W
R/W
Figure
describes WER fields.
Figure
Reference value. Contains the reference value for the watchdog timeout causing an interrupt.
Enable interrupt. When enabled, software should periodically write to WCR to avoid reaching the interrupt
reference value.
0 Disable interrupt.
1 Enable interrupt upon reaching interrupt reference value. If IEN is set when WER[WIE] = 1, an immediate
Watchdog Counter Register (WCR)
Watchdog Event Register (WER)
Reserved, should be cleared.
Watchdog interrupt event.
0 WIRR value has not been reached.
1 WIRR value has been reached.
WIE is cleared by writing a 1 to it. The timer does not negate the interrupt request to the interrupt controller until
WIE is cleared. WIE is set regardless of the state of WIRR[IEN]; however, an interrupt is not asserted to the
controller unless WIRR[IEN] = 1.
15
15
interrupt occurs.
6-11, reports when the watchdog timer reaches the WIRR value.
6-10, contains the 16 most significant bits of the software watchdog counter. Writing
MCF5272 ColdFire
Figure 6-10. Watchdog Counter Register (WCR)
Figure 6-11. Watchdog Event Register (WER)
Table 6-10. WIRR Field Descriptions
Table 6-11. WER Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
0000_0000_0000_0000
0000_0000_0000_0000
MBAR + 0x28C
MBAR + 0x288
—
COUNT
Description
Description
R/W
R/W
System Integration Module (SIM)
1
WIE
0
0
6-13
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