MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 84
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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ColdFire Core
2-16
BCHG
BCLR
BRA
BSET
BSR
BTST
CLR
CMP
CMPA
CMPI
DIVS
DIVU
EOR
EORI
EXT
EXTB
HALT
JMP
JSR
LEA
LINK
LSL
LSR
MAC
MACL
MOVE
Instruction
1
Dy,<ea>x
#<data>,<ea-1>x
Dy,<ea>x
#<data>,<ea-1>x
<label>
Dy,<ea>x
#<data>,<ea-1>x
<label>
Dy,<ea>x
#<data>,<ea-1>x
<ea>y,Dx
<ea>y,Ax
<ea>y,Dx
<ea>y,Dx
<ea-1>y,Dx
<ea>y,Dx
<ea-1>y,Dx
Dy,<ea>x
Dy,<ea>x
#<data>,Dx
#<data>,Dx
Dx
None
<ea-3>y
<ea-3>y
<ea-3>y,Ax
Ax,#<d16>
Dy,Dx
#<data>,Dx
Dy,Dx
#<data>,Dx
Ry,RxSF
Ry,RxSF,<ea-1>y,Rw
<ea>y,<ea>x
Operand Syntax
MCF5272 ColdFire
Table 2-7. User-Mode Instruction Set Summary (continued)
.B,.L
.B,.L
.B,.L
.B,.L
.B,.W
.B,.L
.B,.L
.B,.W
.B,.L
.B,.L
.B,.W,.L
.L
.L
.L
.W
.L
.W
.L
.L
.L
.B →.W
.W →.L
.B →.L
Unsized
Unsized
Unsized
.L
.W
.L
.L
.L
.L
.L + (.W × .W) → .L
.L + (.L × .L) → .L
.L + (.W × .W) → .L, .L
.L + (.L × .L) → .L, .L
.B,.W,.L
Operand Size
®
Integrated Microprocessor User’s Manual, Rev. 3
~(<bit number> of destination) → Z,
Bit of destination
~(<bit number> of destination) → Z;
0 → bit of destination
PC + 2 + d
~(<bit number> of destination) → Z;
1→ bit of destination
SP – 4 → SP; next sequential PC→ (SP); PC + 2 + d
~(<bit number> of destination) → Z
0 → destination
Destination – source
Destination – source
Destination – immediate data
Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient}
Dx /<ea>y → Dx {32-bit quotient}
Signed operation
Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient}
Dx /<ea>y → Dx {32-bit quotient}
Unsigned operation
Source ^ destination → destination
Immediate data ^ destination → destination
Sign-extended destination → destination
Sign-extended destination → destination
Enter halted state
Address of <ea> → PC
SP – 4 → SP; next sequential PC → (SP); <ea> → PC
<ea> → Ax
SP – 4 → SP; Ax → (SP); SP → Ax; SP + d16 → SP
X/C ← (Dx << Dy) ← 0
X/C ← (Dx << #<data>) ← 0
0 → (Dx >> Dy) → X/C
0 → (Dx >> #<data>) → X/C
ACC + (Ry × Rx){<< 1 | >> 1} → ACC
ACC + (Ry × Rx){<< 1 | >> 1} → ACC; (<ea>y{&MASK}) →
Rw
ACC + (Ry × Rx){<< 1 | >> 1} → ACC
ACC + (Ry × Rx){<< 1 | >> 1} → ACC; (<ea-1>y{&MASK}) →
Rw
<ea>y → <ea>x
n
→ PC
Operation
Freescale Semiconductor
n
→ PC
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