MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 311
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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13.5
Any bits in the following registers marked 0 have no function. When the register is a read/write register,
these bits should be cleared.
Some registers are described that control more than one port. In these cases, parentheses indicates to which
port the control bits relate; for example, LM0(0) is the LM0 bit for port 0.
13.5.1
All bits in these registers are read only and are set on hardware or software reset.
The PnB1RRs contain the last four frames of data received on channel B1. (P0B1RR is the B1 channel
data for port 0, P1B1RR is B1 for port 1, and so on.) The data are packed from the least significant byte
(LSB), up to the most significant byte (MSB).
These registers are aligned on longword boundaries from MBAR + 0x300 for P0B1RR to
MBAR + 0x30C for P3B1RR. See
frame and bit alignment within the 32-bit word.
Freescale Semiconductor
Reset
Reset
Field
Field
Addr
R/W
R/W
PLIC Registers
B1 Data Receive Registers (P0B1RR–P3B1RR)
31
15
MBAR + 0x300 (P0B1RR); 0x304 (P1B1RR); 0x308 (P2B1RR); 0x30C (P3B1RR)
MCF5272 ColdFire
Figure 13-13. B1 Receive Data Registers P0B1RR–P3B1RR
1111_1111
1111_1111
Frame 0
Frame 2
Section 13.2.3, “GCI/IDL B- and D-Channel Bit
®
Integrated Microprocessor User’s Manual, Rev. 3
Read Only
Read Only
24
8
23
7
Physical Layer Interface Controller (PLIC)
1111_1111
1111_1111
Frame 1
Frame 3
Alignment,” for the
16
0
13-15
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