MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 438

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

Signal Descriptions
19.13.2 Transmit Data (E_TxD0)
E_TxD0 is the serial output Ethernet data and is only valid during the assertion of Tx_EN. This signal is
used for 10-Mbps Ethernet data. This signal is also used for MII mode data in conjunction with
E_TxD[3:1].
19.13.3 Collision (E_COL)
The E_COL input is asserted upon detection of a collision and remains asserted while the collision persists.
This signal is not defined for full-duplex mode.
19.13.4 Receive Data Valid (E_RxDV)
Asserting the receive data valid (E_RxDV) input indicates that the PHY has valid nibbles present on the
MII. E_RxDV should remain asserted from the first recovered nibble of the frame through to the last
nibble. Assertion of E_RxDV must start no later than the SFD and exclude any EOF.
19.13.5 Receive Clock (E_RxCLK)
The receive clock (E_RxCLK) input provides a timing reference for E_RxDV, E_RxD[3:0], and E_RxER.
19.13.6 Receive Data (E_RxD0)
E_RxD0 is the Ethernet input data transferred from the PHY to the media-access controller when E_RxDV
is asserted. This signal is used for 10-Mbps Ethernet data. This signal is also used for MII mode Ethernet
data in conjunction with E_RxD[3:1].
19.13.7 Transmit Enable (E_TxEN)
The transmit enable (E_TxEN) output indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the first E_TxCLK following the final
nibble of the frame.
19.13.8 Transmit Data (E_TxD[3:1]/PB[10:8])
Ethernet mode: These pins contain the serial output Ethernet data and are valid only during assertion of
E_TxEN in MII mode.
Port B mode: These pins can also be configured as I/O pins PB[10:8].
19.13.9 Receive Data (E_RxD[3:1]/PB[13:11])
Ethernet mode: These pins contain the Ethernet input data transferred from the PHY to the media-access
controller when E_RxDV is asserted in MII mode operation.
Port B mode: These pins can also be configured as I/O pins PB[13:11].
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MCF5272 ColdFire
Integrated Microprocessor User’s Manual, Rev. 3
19-28
Freescale Semiconductor