ADUC7128BSTZ126-RL Analog Devices Inc, ADUC7128BSTZ126-RL Datasheet
ADUC7128BSTZ126-RL
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ADUC7128BSTZ126-RL Summary of contents
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FEATURES Analog I/O Multichannel, 12-bit, 1 MSPS ADC analog-to-digital converter (ADC) channels Fully differential and single-ended modes analog input range REF 10-bit digital-to-analog converter (DAC) 32-bit 21 MHz direct digital synthesis (DDS) Current-to-voltage (I/V) ...
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ADuC7128/ADuC7129 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Timing Specifications .................................................................. 8 Absolute Maximum Ratings.......................................................... 15 ESD Caution................................................................................ 15 Pin Configuration and Function Descriptions........................... 16 Typical ...
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GENERAL DESCRIPTION The ADuC7128/ADuC7129 are fully integrated, 1 MSPS, 12-bit data acquisition systems incorporating a high performance, multi- channel analog-to-digital converter (ADC), DDS with line driver, 16-/32-bit MCU, and Flash/EE memory on a single chip. The ADC consists of up ...
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ADuC7128/ADuC7129 SPECIFICATIONS AV = IOV = 3 3 2.5 V internal reference REF otherwise noted. Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time Accuracy Resolution 3 Integral Nonlinearity ...
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Parameter Relative Accuracy Differential Nonlinearity, +VE Differential Nonlinearity, −VE Offset Error Gain Error Voltage Output Settling Time to 0.1% Line Driver Output Total Harmonic Distortion Output Voltage Swing COMMON MODE AC Mode DC Mode DIFFERENTIAL INPUT IMPEDANCE Leakage Current LD1TX, ...
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ADuC7128/ADuC7129 Parameter 3 LOGIC INPUTS V , Input Low Voltage INL V , Input High Voltage INH Quadrature Encoder Inputs S1/S2/CLR (Schmitt-Triggered Inputs T− V − T− 9 LOGIC OUTPUTS V , Output High Voltage ...
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Line Driver Load 100nF 94Ω LD1TX 27.5µH 118Ω 100nF 94Ω LD2TX 100nF 94Ω LD1TX 57Ω 8.9µH 100nF 94Ω LD2TX Figure 2. Line Driver Load Minimum (Top) and Maximum (Bottom) Rev Page ADuC7128/ADuC7129 ...
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ADuC7128/ADuC7129 TIMING SPECIFICATIONS Table 2. External Memory Write Cycle Parameter Min CLK t 0 MS_AFTER_CLKH t 4 ADDR_AFTER_CLKH t AE_H_AFTER_MS HOLD_ADDR_AFTER_AE_L t HOLD_ADDR_BEFORE_WR_L t WR_L_AFTER_AE_L t 8 DATA_AFTER_WR_L WR_H_AFTER_CLKH t HOLD_DATA_AFTER_WR_H t BEN_AFTER_AE_L ...
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Table 3. External Memory Read Cycle Parameter Min CLK 1/MD Clock t 4 MS_AFTER_CLKH t 4 ADDR_AFTER_CLKH t AE_H_AFTER_MS HOLD_ADDR_AFTER_AE_L t RD_L_AFTER_AE_L t 0 RD_H_AFTER_CLKH DATA_BEFORE_RD_H t 8 DATA_AFTER_RD_H t RELEASE_WS_AFTER_RD_H 0ns 50ns ...
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ADuC7128/ADuC7129 2 I C® Timing Specifications 2 Table Timing in Fast Mode (400 kHz Parameter Description t SCLOCK low pulse width L t SCLOCK high pulse width H t Start condition hold time SHD t ...
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SPI Timing Specifications Table 5. SPI Master Mode Timing (PHASE Mode = 1) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data input setup time ...
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ADuC7128/ADuC7129 Table 6. SPI Master Mode Timing (PHASE Mode = 0) Parameter Description t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t Data output setup before SCLOCK edge ...
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Table 7. SPI Slave Mode Timing (PHASE Mode = 1) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV t ...
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ADuC7128/ADuC7129 Table 8. SPI Slave Mode Timing (PHASE Mode = 0) Parameter Description SCLOCK edge CS t SCLOCK low pulse width SL t SCLOCK high pulse width SH t Data output valid after SCLOCK edge DAV ...
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ABSOLUTE MAXIMUM RATINGS DV = IOV , AGND = REFGND = DACGND = GND 25°C, unless otherwise noted. A Table 9. Parameter AGND to DGND IOV to IOGND AGND ...
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ADuC7128/ADuC7129 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADC5 VDAC ADC9 ADC10 GND ADCNEG AV ADC12/LD1TX ADC13/LD2TX AGND TMS P4.6/SPM10 P4.7/SPM11 P0.0/BM/CMP P0.6/T1/MRST Table 10. ADuC7128 Pin Function Descriptions Pin No. Mnemonic Type 1 ADC5 I 2 VDAC O OUT 3 ADC9 ...
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Pin 1 No. Mnemonic Type DGND S 23 P3.0/PWM1 I/O 24 P3.1/PWM2 I/O 25 P3.2/PWM3 I/O 26 P3.3/PWM4 I/O 27 P0.3/ADC /TRST I/O BUSY 28 RST I 29 P3.4/PWM5 I/O 30 P3.5/PWM6 I/O 31 P0.4/IRQ0/CONVST ...
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ADuC7128/ADuC7129 ADC4 1 ADC5 2 ADC6 3 ADC7 4 VDAC /ADC8 5 OUT ADC9 6 ADC10 7 GND 8 REF ADCNEG ADC12/LD1TX 11 ADC13/LD2TX 12 AGND 13 TMS 14 TDI/P0.1/BLE 15 P2.3/AE 16 P4.6/SPM10/AD14 17 P4.7/SPM11/AD15 ...
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Pin No. Mnemonic 17 P4.6/SPM10/AD14 18 P4.7/SPM11/AD15 19 P0.0/BM/CMP /MS0 OUT 20 P0.6/T1/MRST 21 TCK 22 TDO/P0.2/BHE 23, 53, 67 IOGND 24, 54 IOV DGND 27 P3.0/PWM1/AD0 28 P3.1/PWM2/AD1 29 P3.2/PWM3/AD2 30 P3.3/PWM4/AD3 31 P2.4/MS0 ...
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ADuC7128/ADuC7129 Pin No. Mnemonic 63 P4.2/AD10 64 P4.3/PWM /AD11 TRIP 65 P4.4/AD12 66 P4.5/AD13 68 REFGND 69 V REF 70 DACGND 71, 72 AGND 75 DACV DD 76 ADC11 77 ADC0 78 ADC1 79 ADC2/CMP0 80 ADC3/CMP1 ...
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TYPICAL PERFORMANCE CHARACTERISTICS 1 774kSPS S 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1000 2000 ADC CODES Figure 12. Typical INL Error 1 1MSPS S 0.8 0.6 0.4 0.2 0 ...
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ADuC7128/ADuC7129 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 1161 1162 BIN Figure 18. Code Histogram Plot 0 –20 –40 –60 –80 –100 –120 –140 –160 0 100 FREQUENCY (kHz) Figure 19. Dynamic Performance –20 ...
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TEMPERATURE (°C) Figure 24. Current Consumption vs. Temperature @ 7.85 7.80 7.75 7.70 7.65 7.60 7.55 7.50 7.45 7.40 – ...
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ADuC7128/ADuC7129 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the ...
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OVERVIEW OF THE ARM7TDMI CORE The ARM7 core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8 bits, 16 bits bits. ...
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ADuC7128/ADuC7129 R8_FIQ R8 R9_FIQ R9 R10_FIQ R10 R11_FIQ R11 R12_FIQ R13_ABT R12 R13_SVC R13_FIQ R14_ABT R13 R14_SVC R14_FIQ R14 R15 (PC) SPSR_ABT SPSR_SVC CPSR SPSR_FIQ FIQ SVC ABORT USER MODE MODE MODE ...
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MEMORY ORGANIZATION The ADuC7128/ADuC7129 incorporate three separate blocks of memory SRAM and two on-chip Flash/EE memory. There are 126 kB of on-chip Flash/EE memory available to the user, and the remaining 2 kB are ...
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ADuC7128/ADuC7129 0xFFFFFFFF 0xFFFF0FBC 0xFFFF06BC DDS 0xFFFF0690 0xFFFF0F80 0xFFFF0F18 0xFFFF0688 DAC 0xFFFF0670 0xFFFF0F00 0xFFFF0EA8 0xFFFF0544 ADC 0xFFFF0500 0xFFFF0E80 0xFFFF04A8 0xFFFF0E28 BANDGAP REFERENCE 0xFFFF0480 0xFFFF0E00 0xFFFF0448 0xFFFF0D70 POWER SUPPLY MONITOR 0xFFFF0440 0xFFFF0D00 0xFFFF0434 0xFFFF0C30 PLL AND OSCILLATOR CONTROL 0xFFFF0400 0xFFFF0C00 0xFFFF0394 0xFFFF0B54 ...
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Table 18. ADC Base Address = 0xFFFF0500 Address Name Byte Access Type 0x0500 ADCCON 2 R/W 0x0504 ADCCP 1 R/W 0x0508 ADCCN 1 R/W 0x050C ADCSTA 1 R 0x0510 ADCDAT 4 R 0x0514 ADCRST 1 W Table 19. DAC and ...
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ADuC7128/ADuC7129 Table 25. PLA Base Address = 0xFFFF0B00 Address Name Byte 0x0B00 PLAELM0 2 0x0B04 PLAELM1 2 0x0B08 PLAELM2 2 0x0B0C PLAELM3 2 0x0B10 PLAELM4 2 0x0B14 PLAELM5 2 0x0B18 PLAELM6 2 0x0B1C PLAELM7 2 0x0B20 PLAELM8 2 0x0B24 PLAELM9 ...
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Table 30. QEN Base Address = 0xFFFF0F00 Address Name Byte Access Type 0x0F00 QENCON 2 R/W 0x0F04 QENSTA 1 R 0x0F08 QENDAT 2 R/W 0x0F0C QENVAL 2 R 0x0F14 QENCLR 1 W 0x0F18 QENSET 1 W Table 31. PWM Base ...
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ADuC7128/ADuC7129 ADC CIRCUIT OVERVIEW The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 3 3.6 V supplies and is capable of providing a throughput MSPS when the clock source ...
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SIGN BIT 0 1111 1111 1110 2 × V REF 1LSB = 0 1111 1111 1100 4096 0 1111 1111 1010 0 0000 0000 0001 0 0000 0000 0000 1 1111 1111 1110 1 0000 0000 0100 1 0000 0000 ...
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ADuC7128/ADuC7129 Table 33. ADCCON MMR Bit Designations Bit Value Description 12:10 ADC Clock Speed (fADC = F 000 fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz. 001 fADC/2 (default value). 010 fADC/4. ...
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Table 34. ADCCP MMR Bit Designations Bit Value Description 7:5 Reserved 4:0 Positive Channel Selection Bits 00000 ADC0 00001 ADC1 00010 ADC2 00011 ADC3 00100 ADC4 00101 ADC5 00110 ADC6 00111 ADC7 01000 ADC8 01001 ADC9 01010 ADC10 01011 ...
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ADuC7128/ADuC7129 CONVERTER OPERATION The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. This architecture is described for the three different modes of operation: differential mode, pseudo differential mode, and single-ended mode. Differential Mode The ADuC7128/ADuC7129 contain ...
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Figure 41. Equivalent Analog Input Circuit Conversion Phase: Switches Open, Track Phase: Switches Closed For ac applications, removing high frequency components from the analog input signal ...
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ADuC7128/ADuC7129 BAND GAP REFERENCE The ADuC7128/ADuC7129 provide an on-chip band gap reference of 2.5 V that can be used for the ADC and for the DAC. This internal reference also appears on the V When using the internal reference, a ...
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NONVOLATILE FLASH/EE MEMORY FLASH/EE MEMORY OVERVIEW The ADuC7128/ADuC7129 incorporate Flash/EE memory technology on-chip to provide the user with nonvolatile, in- circuit reprogrammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first ...
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ADuC7128/ADuC7129 FLASH/EE MEMORY SECURITY The 126 kB of Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEE0PRO/FEE0HID MMR protects the 126 kB from being read through JTAG and also in parallel programming ...
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FEE1DAT Register Name Address Default Value FEE1DAT 0xFFFF0E8C 0xXXXX FEE1DAT is a 16-bit data register. FEE1ADR Register Name Address Default Value FEE1ADR 0xFFFF0E90 0x0000 FEE1ADR is a 16-bit address register. FEE1SGN Register Name Address Default Value FEE1SGN 0xFFFF0E98 0xFFFFFF FEE1SGN ...
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ADuC7128/ADuC7129 Table 41. FEExSTA MMR Bit Designations Bit Description 15:6 Reserved. 5 Reserved. 4 Reserved. 3 Flash/EE Interrupt Status Bit. Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in ...
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Table 44. FEE0PRO and FEE0HID MMR Bit Designations Bit Description 31 Read Protection. Cleared by user to protect Block 0. Set by user to allow reading Block 0. 30:0 Write Protection for Page 123 to Page 120, for Page 119 ...
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ADuC7128/ADuC7129 RESET AND REMAP The ARM exception vectors are all situated at the bottom of the memory array, from Address 0x00000000 to Address 0x00000020, as shown in Figure 45. 0xFFFFFFFF KERNEL INTERRUPT SERVICE ROUTINES 0x00080000 INTERRUPT 0x00040000 SERVICE ROUTINES 0x00000020 ...
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OTHER ANALOG PERIPHERALS DAC The ADuC7128/ADuC7129 feature a 10-bit current DAC that can be used to generate user-defined waveforms or sine waves generated by the DDS. The DAC consists of a 10-bit IDAC followed by a current-to-voltage conversion. The current ...
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ADuC7128/ADuC7129 DACEN Register Name Address Default Value DACEN 0xFFFF06B8 0x00 Table 50. DACEN MMR Bit Designations Bit Description 7:1 Reserved. 0 Set the user to enable DAC mode. Set the user to enable DDS ...
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DDSFRQ Register Name Address Default Value DDSFRQ 0xFFFF0694 0x00000000 Table 54. DDSFRQ MMR Bit Designations Bit Description 31:0 Frequency select word (FSW) The DDS frequency is controlled via the DDSFRQ MMR. This MMR contains a 32-bit word (FSW) that controls ...
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ADuC7128/ADuC7129 Comparator Interface The comparator interface consists of a 16-bit MMR, CMPCON, described in Table 57. Table 57. CMPCON MMR Bit Designations Bit Value Name Description 15:11 Reserved. 10 CMPEN Comparator Enable Bit. Set by user to enable the comparator. ...
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OSCILLATOR AND PLL—POWER CONTROL The ADuC7128/ADuC7129 integrate a 32.768 kHz oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator to provide a stable 41.78 MHz clock for the system. The core ...
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ADuC7128/ADuC7129 Table 58. Operating Modes Mode Core Peripherals Active On On Pause On Nap Sleep Stop Table 59. Typical Current Consumption at 25°C PC[2:0] Mode 000 Active 33.1 001 Pause 22.7 010 Nap 3.8 011 Sleep 0.4 ...
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DIGITAL PERIPHERALS PWM GENERAL OVERVIEW The ADuC7128/ADuC7129 integrate a six channel PWM inter- face. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power up, the PWM outputs default to ...
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ADuC7128/ADuC7129 Bit Name Description 6 PWMCP0 16. 32. 64. 128. 256. 5 POINV Set the user to invert all PWM outputs. Cleared by user to use PWM outputs as normal. 4 HOFF High Side ...
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Table 67. PWMCON2 MMR Bit Designations Bit Value Name Description 7 CSEN Set the user to enable the PWM to generate a convert start signal. Cleared by user to disable the PWM convert start signal. 6:4 RSVD ...
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ADuC7128/ADuC7129 Table 68. QENCON MMR Bit Designations Bit Name Description 15:11 RSVD Reserved. 10 FILTEN Set the user to enable filtering on the S1 pin. Cleared by user to disable filtering on the S1 pin. 9 RSVD ...
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QENCLR Register Name Address Default Value QENCLR 0xFFFF0F14 0x00000000 Writing any value to the QENCLR register clears the QENVAL register to 0x0000. The bits in this register are undefined. QENSET Register Name Address Default Value QENSET 0xFFFF0F18 0x00000000 Writing any ...
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ADuC7128/ADuC7129 Table 70. GPIO Pin Function Designations Configuration Port Pin P0.0 GPIO CMP 1 P0.1 GPIO 1 P0.2 GPIO P0.3 GPIO TRST P0.4 GPIO/IRQ0 CONVST P0.5 GPIO/IRQ1 ADC BUSY P0.6 GPIO/T1 MRST P0.7 GPIO ECLK/XCLK 1 P1.0 ...
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GPxDAT Register Name Address Default Value GP0DAT 0xFFFF0D20 0x000000XX GP1DAT 0xFFFF0D30 0x000000XX GP2DAT 0xFFFF0D40 0x000000XX GP3DAT 0xFFFF0D50 0x000000XX GP4DAT 0xFFFF0D60 0x000000XX GPxDAT is a Port x configuration and data register. It configures the direction of the GPIO pins of Port ...
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ADuC7128/ADuC7129 Table 77. UART Signal Descriptions Pin Signal Description SPM0 (Mode 1) SIN0 Serial Receive Data. SPM1 (Mode 1) SOUT0 Serial Transmit Data. SPM2 (Mode 1) RTS0 Request to Send. SPM3 (Mode 1) CTS0 Clear to Send. SPM4 (Mode 1) ...
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Table 80. COMxCON0 MMR Bit Designations Bit Value Name Description 7 DLAB Divisor Latch Access. Set by user to enable access to COMxDIV0 and COMxDIV1 registers. Cleared by user to disable access to COMxDIV0 and COMxDIV1 and enable access to ...
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ADuC7128/ADuC7129 Table 82. COMxIEN0 MMR Bit Designations Bit Name Description 7:4 RSVD Reserved. 3 EDSSI Modem Status Interrupt Enable Bit. Set by user to enable generation of an interrupt if any of COMxSTA1[3:0] are set. Cleared by user. 2 ELSI ...
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Table 85. COMxSTA1 MMR Bit Designations Bit Name Description 7 DCD Data Carrier Detect Ring Indicator. 5 DSR Data Set Ready. 4 CTS Clear to Send. 3 DDCD Delta Data Carrier Detect. Set automatically if DCD changed state ...
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ADuC702x Series Table 87. COMxIEN1 MMR Bit Designations Bit Name 7 ENAM 6 E9BT 5 E9BR 4 ENI 3 E9BD 2 ETD 1 NABP 0 NAB Table 88. COMxIID1 MMR Bit Designations Bit 3:1 Bit 0 Status Bits NINT Priority ...
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SERIAL PERIPHERAL INTERFACE The ADuC7128/ADuC7129 integrate a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry- standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up ...
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ADuC7128/ADuC7129 SPIRX Register Name Address Default Value SPIRX 0xFFFF0A04 0x00 SPIRX is an 8-bit read-only receive register. SPITX Register Name Address Default Value SPITX 0xFFFF0A08 0x00 SPITX is an 8-bit write-only transmit register. Table 91. SPICON MMR Bit Designations Bit ...
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I C-COMPATIBLE INTERFACES The ADuC7128/ADuC7129 support two fully licensed I 2 interfaces. The I C interfaces are both implemented as full hardware master and slave interfaces. Because the two I 2 interfaces are identical, only described ...
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ADuC7128/ADuC7129 I2CxSSTA Register Name Address Default Value I2C0SSTA 0xFFFF0804 0x01 I2C1SSTA 0xFFFF0904 0x01 I2CxSSTA is a status register for the slave channel. Table 93. I2CxSSTA MMR Bit Designations Bit Value Description 31:15 Reserved. These bits should be written as 0. ...
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I2CxSRX Register Name Address Default Value I2C0SRX 0xFFFF0808 0x00 I2C1SRX 0xFFFF0908 0x00 I2CxSRX is a receive register for the slave channel. I2CxSTX Register Name Address Default Value I2C0STX 0xFFFF080C 0x00 I2C1STX 0xFFFF090C 0x00 I2CxSTX is a transmit register for the ...
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ADuC7128/ADuC7129 Bit Description 7 Master Serial Clock Enable Bit. Set by user to enable generation of the serial clock in master mode. Cleared by user to disable serial clock in master mode. 6 Loop-Back Enable Bit. Set by user to ...
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I2CxFIF Register Name Address Default Value I2C0FIF 0xFFFF084C 0x0000 I2C1FIF 0xFFFF094C 0x0000 I2CxFIF is a FIFO status register. Table 95. I2C0FIF MMR Bit Designations Bit Value Description 15:10 Reserved. 9 Master Transmit FIFO Flush. Set by user to flush the ...
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ADuC7128/ADuC7129 Table 96. Element Input/Output PLA Block 0 PLA Block 1 Element Input Output Element 0 P1.0 P1 P1.1 P0 P1.2 P0 P1.3 P0 P1.4 P0 P1.5 P2 ...
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Table 99. PLACLK MMR Bit Designations Bit Value Description 7 Reserved. 6:4 Block 1 Clock Source Selection. 000 GPIO Clock on P0.5. 001 GPIO Clock on P0.0. 010 GPIO Clock on P0.7. 011 HCLK. 100 OCLK. 101 Timer1 Overflow. 110 ...
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ADuC7128/ADuC7129 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 30 interrupt sources on the ADuC7128/ADuC7129 controlled by the interrupt controller. Most interrupts are generated from the on-chip peripherals, such as ADC and UART. Two additional interrupt sources are generated from external ...
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Programmed Interrupts As the programmed interrupts are nonmaskable, they are controlled by the SWICFG register that writes into both the IRQSTA and IRQSIG registers and/or FIQSTA and FIQSIG registers at the same time. The 32-bit register dedicated to software interrupt ...
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ADuC7128/ADuC7129 The Timer0 interface consists of six MMRs, shown in Table 108. Table 108. Timer0 Interface MMRs Name Description T0LD A 16-bit register that holds the 16-bit value loaded into the counter. Available only in 16-bit mode. T0CAP A 16-bit ...
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TIMER1—GENERAL-PURPOSE TIMER 32-BIT LOAD 32.768kHz OSCILLATOR CORE CLOCK PRESCALER FREQUENCY 1, 16, 256, UP/DOWN COUNTER OR 32768 GPIO GPIO IRQ[31:0] CAPTURE Figure 56. Timer1 Block Diagram Timer1 is a 32-bit general-purpose count down or count up timer with a programmable ...
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ADuC7128/ADuC7129 Table 111. T1CON MMR Bit Designations Bit Value Description 31:18 Reserved. Should be set the user. 17 Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time ...
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TIMER2—WAKE-UP TIMER EXTERNAL 32kHz OSCILLATOR PRESCALER INTERNAL 32kHz 1, 16, 256, OSCILLATOR OR 32768 CORE CLOCK Figure 57. Timer2 Block Diagram Timer2 is a 32-bit wake-up timer, count down or count up, with a programmable prescaler. The prescaler is clocked ...
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ADuC7128/ADuC7129 Table 113. T2CON MMR Bit Designations Bit Value Description 31:11 Reserved. 10:9 Clock Source Select. 00 Core Clock (Default). 01 Internal 32.768 kHz Oscillator. 10 External 32.768 kHz Watch Crystal. 11 External 32.768 kHz Watch Crystal. 8 Count Up. ...
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TIMER3—WATCHDOG TIMER 16-BIT LOAD 16-BIT PRESCALER LOW POWER UP/DOWN 32.768kHz 1, 16, OR 256 COUNTER TIMER3 VALUE Figure 58. Timer3 Block Diagram Timer3 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover ...
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ADuC7128/ADuC7129 Table 115. T3CON MMR Bit Designations Bit Value Description 16:9 These bits are reserved and should be written user code. 8 Count Up/Down Enable. Set by user code to configure Timer3 to count up. Cleared by ...
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TIMER4—GENERAL-PURPOSE TIMER 32-BIT LOAD 32.768kHz OSCILLATOR CORE CLOCK PRESCALER FREQUENCY 1, 16, 256, UP/DOWN COUNTER OR 32768 GPIO GPIO IRQ[31:0] CAPTURE Figure 60. Timer4 Block Diagram Timer4 is a 32-bit, general-purpose count down or count up timer with a programmable ...
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ADuC7128/ADuC7129 Table 117. T4CON MMR Bit Designations Bit Value Description 31:18 Reserved. Set by user Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an ...
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EXTERNAL MEMORY INTERFACING The ADuC7129 is the only model in the series that features an external memory interface. The external memory interface requires a larger number of pins. This is why it is only available on larger pin count packages. ...
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ADuC7128/ADuC7129 The XMxPAR are registers that define the protocol used for accessing the external memory for each memory region. Table 121. XMxPAR MMR Bit Designations Bit Description 15 Enable Byte Write Strobe. This bit is only used for two, 8-bit ...
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HCLK AD16:0 ADDRESS EXTRA ADDRESS HOLD TIME (BIT 10) MSx AE RS Figure 63. External Memory Read Cycle with Address Hold and Bus Turn Cycles HCLK AD16:0 ADDRESS EXTRA ADDRESS HOLD TIME (BIT 10) MSx AE WS Figure 64. External ...
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ADuC7128/ADuC7129 HCLK AD16:0 MSx AE WS ADDRESS 1 ADDRESS WAIT STATE (BIT 14 TO BIT 12) Figure 65. External Memory Write Cycle with Wait States Rev Page DATA 1 WRITE STROBE WAIT STATE (BIT 7 ...
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HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES The ADuC7128/ADuC7129 operational power supply voltage range is 3 3.6 V. Separate analog and digital power supply pins (AV and IOV , respectively) allow relatively free of noisy digital signals ...
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ADuC7128/ADuC7129 In these cases, tie the AGND pins and IOGND pins of the ADuC7128/ADuC7129 to the analog ground plane, as shown in Figure 69b. In systems with only one ground plane, ensure that the digital and analog components are physically ...
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POWER-ON RESET OPERATION An internal power-on reset (POR) is implemented on the ADuC7128/ADuC7129. For LV below 2.45 V, the internal DD POR holds the ADuC7128/ADuC7129 in reset above 2. internal timer times out for typically 64 ...
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ADuC7128/ADuC7129 DEVELOPMENT TOOLS An entry level, low cost development system is available for the ADuC7128/ADuC7129. This system consists of the following PC-based (Windows® compatible) hardware and software development tools. Hardware • ADuC7128/ADuC7129 evaluation board • Serial port programming cable • ...
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OUTLINE DIMENSIONS 9.00 BSC SQ PIN 1 INDICATOR TOP VIEW 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 0.80 SEATING 0.50 BSC PLANE 1.45 1.40 1.35 SEATING PLANE VIEW A ROTATED 90° CCW 0.60 MAX 0.60 MAX 49 48 8.75 ...
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... Temperature Range 2 ADUC7128BCPZ126 −40°C to +125°C ADUC7128BCPZ126-RL 2 −40°C to +125°C 2 ADUC7128BSTZ126 −40°C to +125°C 2 ADUC7128BSTZ126-RL −40°C to +125°C 2 ADUC7129BSTZ126 −40°C to +125°C ADUC7129BSTZ126-RL 2 −40°C to +125°C 2 EVAL-ADUC7128QSPZ 1 Reel quantities are 2,500 for the LFCSP and 1,000 for the LQFP. ...