ADUC7128BSTZ126-RL Analog Devices Inc, ADUC7128BSTZ126-RL Datasheet - Page 69

• Manufacturer Part Number: ADUC7128BSTZ126-RL
• Description: IC DAS MCU ARM7 ADC/DDS 64-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BSTZ126-RL

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: ADUC7128BSTZ126-RLTR

I2CxFIF Register
Name
I2C0FIF
I2C1FIF
I2CxFIF is a FIFO status register.
Table 95. I2C0FIF MMR Bit Designations
Bit
15:10
9
8
7:6
5:4
3:2
1:0
PROGRAMMABLE LOGIC ARRAY (PLA)
The ADuC7128/ADuC7129 integrate a fully programmable
logic array (PLA) that consists of two independent but
interconnected PLA blocks. Each block consists of eight PLA
elements, giving a total of 16 PLA elements.
A PLA element contains a two input look-up table that can be
configured to generate any logic output function based on two
inputs and a flip-flop as represented in Figure 54.
Value
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0
1
Address
0xFFFF084C
0xFFFF094C
Description
Reserved.
Master Transmit FIFO Flush.
Slave Transmit FIFO Flush.
Master Rx FIFO Status Bits.
FIFO Empty.
Byte Written to FIFO.
1 Byte in FIFO.
FIFO Full.
Master Tx FIFO Status Bits.
FIFO Empty.
Byte Written to FIFO.
1 Byte in FIFO.
FIFO Full.
Slave Rx FIFO Status Bits.
FIFO Empty.
Byte Written to FIFO.
1 Byte in FIFO.
FIFO Full.
Slave Tx FIFO Status Bits.
FIFO Empty.
Byte Written to FIFO.
1 Byte in FIFO.
FIFO full.
2
3
Set by user to flush the master Tx FIFO.
Cleared automatically once the master Tx FIFO is flushed. This bit also flushes the slave receive FIFO.
Set by user to flush the slave Tx FIFO.
Cleared automatically once the slave Tx FIFO is flushed.
Figure 54. PLA Element
A
B
LOOK-UP
TABLE
Default Value
0x0000
0x0000
4
Access
R
R
Rev. 0 | Page 69 of 92
In total, 30 GPIO pins are available on the ADuC7128/ADuC7129
for the PLA. These include 16 input pins and 14 output pins.
They need to be configured in the GPxCON register as PLA
pins before using the PLA. Note that the comparator output is
also included as one of the 16 input pins.
The PLA is configured via a set of user MMRs and the output(s)
of the PLA can be routed to the internal interrupt system, to the
CONVST signal of the ADC, to an MMR, or to any of the
16 PLA output pins.
The interconnection between the two blocks is supported by
connecting the output of Element 7 of Block 1 fed back to the
Input 0 of Mux 0 of Element 0 of Block 0, and the output of
Element 7 of Block 0 is fed back to the Input 0 of Mux 0 of
Element 0 of Block 1.
ADuC7128/ADuC7129