MAXQ7667AACM/V+ Maxim Integrated Products, MAXQ7667AACM/V+ Datasheet - Page 16

• Manufacturer Part Number: MAXQ7667AACM/V+
• Description: IC MCU-BASED DAS 16BIT 48-LQFP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7667AACM/V+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 16
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 2.75 V
• Data Converters: A/D 5x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Processor Series: MAXQ7667
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: UART, JTAG, LIN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MAXQ7667EVKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16-Bit, RISC, Microcontroller-Based,
Ultrasonic Distance-Measuring System
The ultrasonic distance-measurement peripherals in the
MAXQ7667 include a burst signal generator for
acoustic transmission and mixed signal circuits for
amplifying and digitizing echo signals ranging between
25kHz and 100kHz. The burst signal is a square wave
with adjustable duty cycle and pulse count. The burst is
derived either directly from the system clock or from a
programmable PLL locked to the system clock. The
MAXQ7667 effectively digitizes the echo signals
received at the ECHOP and ECHON inputs using an
LNA, sigma-delta ADC with variable analog gain ampli-
fier, noise-limiting digital bandpass filter, digital full-
wave rectifier, and a digital lowpass filter (see the
Typical Application Circuit/Functional Diagram ). The
device detects echo signals at the burst frequency with
amplitudes ranging from 10µV
greater than 100mV
ly clipped but do not saturate the receiver. To optimize
echo reception, the clock used for processing the echo
locks to the burst frequency. The MAXQ7667’s burst
generator can generate higher frequencies, but the
maximum usable frequency for the echo receive path is
100kHz . For applications requiring transducer frequen-
cies above 100kHz, implement an external echo
receive path. The SAR ADC can then digitize the fil-
tered echo envelope.
An integrated 16-bit RISC µC (MAXQ20) provides tim-
ing control, signal processing, and data I/O. The 16-bit
Harvard architecture RISC core executes most instruc-
tions in a single clock cycle from instruction fetch to
cycle completion. The MAXQ20 provides optimal per-
formance for noise-sensitive analog applications.
Figure 1. Burst Transmission Stage
16
24kΩ
33nF
R1
C1
______________________________________________________________________________________
C2
330pF
FILT
(f
P-P
SYSTEM
CLOCK
SYSCLK
PLLF[10:9]:PLLC[1:0]
Detailed Description
and less than 2V
)
BTRN[15:12]:BDIV[3:0]
PLL
PLLF[8:0]
P-P
to 100mV
BTRN.10:BCKS
1
0
P-P
are internal-
P-P
. Echoes
BPH[9:0]
RECEIVE CLOCK
BURST CLOCK
GENERATOR
PRESCALE
BTRN[7:0]:BCNT[7:0]
MAXQ7667
The MAXQ7667 includes a 13.5MHz RC oscillator,
external crystal oscillator, watchdog timer, schedule
timer, three general-purpose Type 2 timers/counters,
two 8-bit GPIO ports, SPI interface, JTAG interface, LIN
capable UART interface, 12-bit SAR ADC with five mul-
tiplexed input channels, supply-voltage monitors, and a
voltage reference for communication, diagnostics, and
miscellaneous support.
The MAXQ7667 provides a square-wave burst signal at
the BURST output. Use the burst control to transmit an
ultrasonic signal. Typical applications use the burst sig-
nal to switch an external transistor that drives a high-
voltage transformer, which excites the transducer (see
the Typical Application Circuit/Functional Diagram ).
Use software to configure the duty cycle, frequency,
number of pulses, and drive current of the burst. See
Section 17 of the MAXQ7667 User’s Guide .
Derive the burst signal either directly from the system
clock or from a programmable oscillator phase locked
to the system clock (Figure 1). Using the system clock
limits the burst frequency to one of 16 choices. Integer
division of the system clock generates these 16 fre-
quencies. The PLL allows a fractional division of the
system clock. Any frequency within the PLL range is
selectable to a resolution of 0.13% or better.
When using the internal PLL, connect external filter
components (C1, R1, and C2) to FILT as shown in
Figure 1. These components filter the analog voltage
that controls the VCO in the PLL. The filter component
values shown in the figure are suitable for the entire
PLL frequency range.
BPH.15:BSTT
RECEIVE
CLOCK
ECHO
PWM
DIAGNOSTIC
BTRN.8:BGT
2mV
BURST
P-P
BTRN.11:BPOL
Burst Controller
BTRN.9:BTRI
BPH.14:BDS
BURST