ATMEGA644-20PU Atmel, ATMEGA644-20PU Datasheet - Page 75
![IC AVR MCU FLASH 64K 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA644-20PU
Manufacturer Part Number
ATMEGA644-20PU
Description
IC AVR MCU FLASH 64K 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN, ATAVRRZUSBSTICK, ATAVRRZ201
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
20MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA644-20PU
Manufacturer:
Atmel
Quantity:
1 930
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12.3.2
2593N–AVR–07/10
Alternate Functions of Port B
The Port B pins with alternate functions are shown in
Table 12-6.
The alternate pin configuration is as follows:
• SCK/PCINT15 – Port B, Bit 7
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI0 is
enabled as a master, the data direction of this pin is controlled by DDB7. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB7 bit.
PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external interrupt
source.
• MISO/PCINT14 – Port B, Bit 6
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a
master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is
enabled as a slave, the data direction of this pin is controlled by DDB6. When the pin is forced to
be an input, the pull-up can still be controlled by the PORTB6 bit.
PCINT14, Pin Change Interrupt source 14: The PB6 pin can serve as an external interrupt
source.
Port Pin
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Alternate Functions
SCK (SPI Bus Master clock input)
PCINT15 (Pin Change Interrupt 15)
MISO (SPI Bus Master Input/Slave Output)
PCINT14 (Pin Change Interrupt 14)
MOSI (SPI Bus Master Output/Slave Input)
PCINT13 (Pin Change Interrupt 13)
SS (SPI Slave Select input)
OC0B (Timer/Conter 0 Output Compare Match B Output)
PCINT12 (Pin Change Interrupt 12)
AIN1 (Analog Comparator Negative Input)
OC0A (Timer/Conter 0 Output Compare Match A Output)
PCINT11 (Pin Change Interrupt 11)
AIN0 (Analog Comparator Positive Input)
INT2 (External Interrupt 2 Input)
PCINT10 (Pin Change Interrupt 10)
T1 (Timer/Counter 1 External Counter Input)
CLKO (Divided System Clock Output)
PCINT9 (Pin Change Interrupt 9)
T0 (Timer/Counter 0 External Counter Input)
XCK0 (USART0 External Clock Input/Output)
PCINT8 (Pin Change Interrupt 8)
Port B Pins Alternate Functions
Table
12-6.
ATmega644
75
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