PIC18LF248-I/SP Microchip Technology, PIC18LF248-I/SP Datasheet - Page 170
![IC MCU CAN FLASH 8K LP 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF248-I/SP
Manufacturer Part Number
PIC18LF248-I/SP
Description
IC MCU CAN FLASH 8K LP 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18LF242-ISO.pdf
(36 pages)
3.PIC18F248-ISO.pdf
(402 pages)
4.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18LF248-I/SP
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
22
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- PIC16F616T-ISL PDF datasheet
- PIC18LF242-ISO PDF datasheet #2
- PIC18F248-ISO PDF datasheet #3
- PIC18F248-ISO PDF datasheet #4
- Current page: 170 of 402
- Download datasheet (7Mb)
17.4.6.1
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition, or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I
not be released.
In Master Transmitter mode, serial data is output
through SDA while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate receive bit. Serial
data is received via SDA while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an Acknowledge bit is transmitted.
Start and Stop conditions indicate the beginning and
end of transmission.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I
Section 17.4.7 “Baud Rate Generator” for more
details.
DS41159E-page 168
PIC18FXX8
I
2
C Master Mode Operation
2
C operation. See
2
C bus will
A typical transmit sequence would go as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The MSSP module generates an interrupt at the
11. The user generates a Stop condition by setting
12. Interrupt is generated once the Stop condition is
The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2<0>).
SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
The user loads the SSPBUF with the slave
address to transmit.
Address is shifted out the SDA pin until all 8 bits
are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The user loads the SSPBUF with eight bits of
data.
Data is shifted out the SDA pin until all 8 bits are
transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
end of the ninth clock cycle by setting the SSPIF
bit.
the Stop Enable bit PEN (SSPCON2<2>).
complete.
© 2006 Microchip Technology Inc.
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