PIC18LF248-I/SP Microchip Technology, PIC18LF248-I/SP Datasheet - Page 208
![IC MCU CAN FLASH 8K LP 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF248-I/SP
Manufacturer Part Number
PIC18LF248-I/SP
Description
IC MCU CAN FLASH 8K LP 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18LF242-ISO.pdf
(36 pages)
3.PIC18F248-ISO.pdf
(402 pages)
4.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18LF248-I/SP
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
22
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- PIC16F616T-ISL PDF datasheet
- PIC18LF242-ISO PDF datasheet #2
- PIC18F248-ISO PDF datasheet #3
- PIC18F248-ISO PDF datasheet #4
- Current page: 208 of 402
- Download datasheet (7Mb)
19.2.2
This section describes the CAN Transmit Buffer
registers and their associated control registers.
REGISTER 19-4:
DS41159E-page 206
PIC18FXX8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
CAN TRANSMIT BUFFER
REGISTERS
TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS
bit 7
Legend:
R = Readable bit
-n = Value at POR
Unimplemented: Read as ‘0’
TXABT: Transmission Aborted Status bit
1 = Message was aborted
0 = Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit
1 = Requests sending a message. Clears the TXABT, TXLARB and TXERR bits.
0 = Automatically cleared when the message is successfully sent
Unimplemented: Read as ‘0’
TXPRI1:TXPRI0: Transmit Priority bits
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
Note:
Note:
U-0
—
Clearing this bit in software while the bit is set will request a message abort.
These bits set the order in which the Transmit Buffer will be transferred. They do
not alter the CAN message identifier.
TXABT
R-0
TXLARB
W = Writable bit
‘1’ = Bit is set
R-0
TXERR
R-0
TXREQ
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
© 2006 Microchip Technology Inc.
x = Bit is unknown
TXPRI1
R/W-0
TXPRI0
R/W-0
bit 0
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