PIC18LF248-I/SP Microchip Technology, PIC18LF248-I/SP Datasheet - Page 308
![IC MCU CAN FLASH 8K LP 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF248-I/SP
Manufacturer Part Number
PIC18LF248-I/SP
Description
IC MCU CAN FLASH 8K LP 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18LF242-ISO.pdf
(36 pages)
3.PIC18F248-ISO.pdf
(402 pages)
4.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18LF248-I/SP
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
22
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- PIC16F616T-ISL PDF datasheet
- PIC18LF242-ISO PDF datasheet #2
- PIC18F248-ISO PDF datasheet #3
- PIC18F248-ISO PDF datasheet #4
- Current page: 308 of 402
- Download datasheet (7Mb)
MOVFF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (destin.)
Description:
Words:
Cycles:
Example:
DS41159E-page 306
PIC18FXX8
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
REG1
REG2
REG1
REG2
Q1
No dummy
register ‘f’
operation
Move f to f
[ label ]
0
0
(f
None
The contents of source register ‘f
moved to destination register ‘f
Location of source ‘f
in the 4096-byte data space (000h to
FFFh) and location of destination ‘f
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
The MOVFF instruction should not be
used to modify interrupt settings while
any interrupt is enabled (see page 77).
2
2 (3)
MOVFF
s
Read
(src)
read
)
1100
1111
No
Q2
f
f
=
=
=
=
s
d
f
d
4095
4095
0x33
0x11
0x33
0x33
MOVFF f
REG1, REG2
ffff
ffff
operation
Process
Data
No
Q3
s
s
,f
’ can be anywhere
ffff
ffff
d
register ‘f’
operation
(dest)
Write
d
No
Q4
ffff
ffff
’.
s
’ are
d
’
s
d
MOVLB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
BSR register
BSR register
Q1
Read literal
Move Literal to Low Nibble in BSR
[ label ]
0
k
None
The 8-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
1
1
MOVLB
0000
Q2
‘k’
k
=
=
BSR
© 2006 Microchip Technology Inc.
255
0x02
0x05
MOVLB k
5
0001
Process
Data
Q3
kkkk
literal ‘k’ to
Write
BSR
Q4
kkkk
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