MC908QY8CDWE Freescale Semiconductor, MC908QY8CDWE Datasheet - Page 183

• Manufacturer Part Number: MC908QY8CDWE
• Description: IC MCU 8BIT 8K FLASH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QY8CDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Processor Series: HC08QY
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.7 I/O Signals
The TIM module can share its pins with the general-purpose I/O pins. See
that are shared.
16.7.1 TIM Channel I/O Pins (TCH3:TCH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
TCH0 and TCH2 can be configured as buffered output compare or buffered PWM pins.
16.7.2 TIM Clock Pin (TCLK)
TCLK is an external clock input that can be the clock source for the counter instead of the prescaled
internal bus clock. Select the TCLK input by writing 1s to the three prescaler select bits, PS[2:0].
(See
Interface Module
frequency ÷ 2.
16.8 Registers
The following registers control and monitor operation of the TIM:
16.8.1 TIM Status and Control Register
The TIM status and control register (TSC) does the following:
TOF — TIM Overflow Flag Bit
Freescale Semiconductor
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This read/write flag is set when the counter reaches the modulo value programmed in the TIM counter
modulo registers. Clear TOF by reading the TSC register when TOF is set and then writing a 0 to TOF.
If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no
16.8.1 TIM Status and Control
TIM status and control register (TSC)
TIM control registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0 through TSC3)
TIM channel registers (TCH0H:TCH0L through TCH3H:TCH3L)
Enables TIM overflow interrupts
Flags TIM overflows
Stops the counter
Resets the counter
Prescales the counter clock
Reset:
Read:
Write:
Characteristics. The maximum TCLK frequency is the least of 4 MHz or bus
Bit 7
TOF
0
0
Figure 16-4. TIM Status and Control Register (TSC)
= Unimplemented
TOIE
6
0
Register.) The minimum TCLK pulse width is specified in
MC68HC908QB8 Data Sheet, Rev. 3
TSTOP
5
1
TRST
0
4
0
3
0
0
PS2
2
0
Figure 16-1
PS1
1
0
Bit 0
PS0
0
for the port pins
18.16 Timer
I/O Signals
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