MC908JL16CSPE Freescale Semiconductor, MC908JL16CSPE Datasheet - Page 117

• Manufacturer Part Number: MC908JL16CSPE
• Description: IC MCU 16K FLASH 8MHZ 32-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL16CSPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• For Use With: DEMO908JL16E - BOARD DEMO FOR MC908JL16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.8.3 Multi-Master IIC Master Control Register (MIMCR)
MMALIF — Multi-Master Arbitration Lost Interrupt Flag
MMNAKIF — No Acknowledge Interrupt Flag
MMBB — Bus Busy Flag
MMAST — Master Control Bit
MMRW — Master Read/Write
Freescale Semiconductor
This flag is set when software attempt to set MMAST but the MMBB has been set by detecting the start
condition on the lines or when the MMIIC is transmitting a "1" to SDA line but detected a "0" from SDA
line in master mode – an arbitration loss. This bit generates an interrupt request to the CPU if the
MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or by reset.
This flag is only set in master mode (MMAST = 1) when there is no acknowledge bit detected after one
data byte or calling address is transferred. This flag also clears MMAST. MMNAKIF generates an
interrupt request to CPU if the MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it or
by reset.
This flag is set after a start condition is detected (bus busy), and is cleared when a stop condition (bus
idle) is detected. Reset clears this bit.
This bit is set to initiate a master mode transfer. In master mode, the module generates a start condition
to the SDA and SCL lines, followed by sending the calling address stored in MMADR. When the
MMAST bit is cleared by MMNAKIF set (no acknowledge) or by software, the module generates the
stop condition to the lines after the current byte is transmitted. If an arbitration loss occurs (MMALIF =
1), the module reverts to slave mode by clearing MMAST, and releasing SDA and SCL lines
immediately. This bit is cleared by writing “0” to it or by reset.
This bit will be transmitted out as bit 0 of the calling address when the module sets the MMAST bit to
enter master mode. The MMRW bit determines the transfer direction of the data bytes that follows.
When it is "1", the module is in master receive mode. When it is "0", the module is in master transmit
mode. Reset clears this bit.
1 = Lost arbitration in master mode
0 = No arbitration lost
1 = No acknowledge bit detected
0 = Acknowledge bit detected
1 = Start condition detected
0 = Stop condition detected or MMIIC is disabled
1 = Master mode operation
0 = Slave mode operation
1 = Master mode receive
0 = Master mode transmit
Address: $0040
Reset:
Read: MMALIF
Write:
Figure 8-6. Multi-Master IIC Master Control Register (MIMCR)
Bit 7
0
0
= Unimplemented
MMNAKIF
6
0
0
MC68HC908JL16 Data Sheet, Rev. 1.1
MMBB
5
0
MMAST
4
0
MMRW
3
0
MMBR2
2
0
MMBR1
1
0
Multi-Master IIC Registers
MMBR0
Bit 0
0
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