MC9S08EL16CTJ Freescale Semiconductor, MC9S08EL16CTJ Datasheet - Page 122
![MCU 16KB FLASH SLIC 20TSSOP](/photos/12/26/122655/mc9s08el16ctj_sml.jpg)
MC9S08EL16CTJ
Manufacturer Part Number
MC9S08EL16CTJ
Description
MCU 16KB FLASH SLIC 20TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.DEMO9S08EL32.pdf
(356 pages)
Specifications of MC9S08EL16CTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
S08EL
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI, I2C, SLIC
Maximum Clock Frequency
200 KHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08EL32AUTO, DEMO9S08EL32
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
DEMO9S08EL32 - BOARD DEMO FOR 9S08 EL MCUDEMO9S08EL32AUTO - DEMO BOARD EL32 AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Internal Clock Source (S08ICSV2)
8.3.3
8.3.4
122
IREFST
CLKST
Field
TRIM
Field
3-2
7:0
7:5
4
Reset:
Reset:
POR:
POR:
W
W
R
R
ICS Trim Register (ICSTRM)
ICS Status and Control (ICSSC)
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
Reserved, should be cleared.
Internal Reference Status — The IREFST bit indicates the current source for the reference clock. The IREFST
bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock
domains.
0 Source of reference clock is external clock.
1 Source of reference clock is internal clock.
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00
01
10
11
Output of FLL is selected.
FLL Bypassed, Internal reference clock is selected.
FLL Bypassed, External reference clock is selected.
Reserved.
U
1
7
7
0
0
0
Table 8-5. ICS Status and Control Register Field Descriptions
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Figure 8-6. ICS Status and Control Register (ICSSC)
Table 8-4. ICS Trim Register Field Descriptions
U
0
0
0
0
6
6
Figure 8-5. ICS Trim Register (ICSTRM)
U
0
0
0
0
5
5
IREFST
U
0
1
1
4
4
Description
Description
TRIM
U
0
0
0
3
3
CLKST
U
0
0
0
2
2
OSCINIT
Freescale Semiconductor
U
0
0
0
1
1
FTRIM
U
U
0
0
0
0
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