MC9S08EL16CTJ Freescale Semiconductor, MC9S08EL16CTJ Datasheet - Page 81

• Manufacturer Part Number: MC9S08EL16CTJ
• Description: MCU 16KB FLASH SLIC 20TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08EL16CTJ

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP
• Processor Series: S08EL
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, I2C, SLIC
• Maximum Clock Frequency: 200 KHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08EL32AUTO, DEMO9S08EL32
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: DEMO9S08EL32 - BOARD DEMO FOR 9S08 EL MCUDEMO9S08EL32AUTO - DEMO BOARD EL32 AUTO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3
Port A[3:0], port B[3:0] and port C pins can be configured as external interrupt inputs and as an external
mean of waking the MCU from stop3 or wait low-power modes.
The block diagram for each port interrupt logic is shown
Writing to the PTxPSn bits in the port interrupt pin select register (PTxPS) independently enables or
disables each port pin. Each port can be configured as edge sensitive or edge and level sensitive based on
the PTxMOD bit in the port interrupt status and control register (PTxSC). Edge sensitivity can be software
programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or
edge and level sensitivity is selected using the PTxESn bits in the port interrupt edge select register
(PTxES).
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled port inputs must be at the
deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic 1 (the
deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising
edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during
the next cycle.
6.3.1
A valid edge on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt request
will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in PTxSC.
6.3.2
A valid edge or level on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt
request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in
PTxSC provided all enabled port inputs are at their deasserted levels. PTxIF will remain set if any enabled
port pin is asserted while attempting to clear by writing a 1 to PTxACK.
Freescale Semiconductor
PIxn
PIxn
PTxESn
PTxS0
Pin Interrupts
1
0
1
0
S
S
Edge Only Sensitivity
Edge and Level Sensitivity
PTxPS0
PTxPSn
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Figure 6-2. Port Interrupt Block Diagram
PTxMOD
V
DD
D
CK
CLR
Q
Figure
INTERRUPT FF
PORT
6-2.
PTxACK
RESET
STOP
Chapter 6 Parallel Input/Output Control
SYNCHRONIZER
STOP BYPASS
BUSCLK
PTxIE
PTxIF
PTx
INTERRUPT
REQUEST
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