MC9S08EL16CTJ Freescale Semiconductor, MC9S08EL16CTJ Datasheet - Page 195
![MCU 16KB FLASH SLIC 20TSSOP](/photos/12/26/122655/mc9s08el16ctj_sml.jpg)
MC9S08EL16CTJ
Manufacturer Part Number
MC9S08EL16CTJ
Description
MCU 16KB FLASH SLIC 20TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.DEMO9S08EL32.pdf
(356 pages)
Specifications of MC9S08EL16CTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
S08EL
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI, I2C, SLIC
Maximum Clock Frequency
200 KHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08EL32AUTO, DEMO9S08EL32
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
DEMO9S08EL32 - BOARD DEMO FOR 9S08 EL MCUDEMO9S08EL32AUTO - DEMO BOARD EL32 AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1
12.3.5
SLIC state vector register (SLCSV) is provided to substantially decrease the CPU overhead associated
with servicing interrupts while under operation of a LIN protocol. It provides an index offset that is directly
related to the LIN module’s current state, which can be used with a user supplied jump table to rapidly
enter an interrupt service routine. This eliminates the need for the user to maintain a duplicate state
machine in software.
Freescale Semiconductor
SLCACT
SLCACT may not be clear during all idle times of the bus. For example, if IMSG was used to ignore the data interrupts of an
extended message frame, SLCACT will remain set until another LIN message is received and either the RX Message Buffer
Full Checksum OK (SLCSV = 0x10) or the TX Message Buffer Empty Checksum Transmitted (SLCSV = 0x08) interrupt
sources are asserted and cleared. When clear, SLCACT always indicates times when the SLIC module is not active, but it is
possible for the SLIC module to be not active with SLCACT set. SLCACT has no meaning in BTM mode.
INITACK
SLCF
Field
7
5
0
Reset
1
W
R
SLIC State Vector Register (SLCSV)
SLIC Active (Oscillator Trim Blocking Semaphore) — SLCACT is used to indicate if it is safe to trim the
oscillator based upon current SLIC activity in LIN mode. This bit indicates that the SLIC module might be currently
receiving a message header, synchronization byte, ID byte, or sending or receiving data bytes. This bit is
read-only. This bit has no meaning in BTM mode (BTM =1).
0 SLIC module not active (safe to trim oscillator) SLCACT is cleared by the SLIC module only upon assertion of
1 SLIC module activity (not safe to trim oscillator)
Initialization Mode Acknowledge — INITACK indicates whether the SLIC module is in the reset mode as a
result of writing INITREQ in SLCC1. INITACK = 1 causes all SLIC register bits (except SLCWCM: write once) to
be held in their reset state and become not writable until INITACK has been cleared. Clear INITACK by clearing
INITREQ in SLCC1. After INITACK is cleared, the SLIC module proceeds to SLIC DISABLED mode (see
Figure
operating mode. INITACK is a read-only bit.
0 Normal operation
1 SLIC module is in reset state
SLIC Interrupt Flag — The SLCF interrupt flag indicates if a SLIC module interrupt is pending. If set, the SLCSV
is then used to determine what interrupt is pending. This flag is cleared by writing a 1 to the bit. If additional
interrupt sources are pending, the bit will be automatically set to 1 again by the SLIC.
0 No SLIC interrupt pending
1 SLIC interrupt pending
SLCACT
the RX Message Buffer Full Checksum OK (SLCSV = 0x10) or the TX Message Buffer Empty Checksum
Transmitted (SLCSV = 0x08) interrupt sources.
SLCACT is automatically set to 1 if a falling edge is seen on the SLCRX pin and has successfully been passed
through the digital RX filter. This edge is the potential beginning of a LIN message frame.
0
7
12-2) in which the other SLIC register bits are writable and can be configured to the desired SLIC
= Unimplemented or Reserved
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
6
0
0
Figure 12-8. SLIC Status Register (SLCS)
Table 12-6. SLCS Field Descriptions
INITACK
1
5
4
0
0
Description
0
0
3
2
0
0
0
0
1
SLCF
0
0
197
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