C8051F341-GQ Silicon Laboratories Inc, C8051F341-GQ Datasheet
C8051F341-GQ
Specifications of C8051F341-GQ
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C8051F341-GQ Summary of contents
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Analog Peripherals - 10-Bit ADC ('F340/1/2/3/4/5/6/7 only 200 ksps • Built-in analog multiplexer with single-ended and • differential mode VREF from external pin, internal reference • Built-in temperature sensor • External conversion start input option • ...
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C8051F340/1/2/3/4/5/6/7/8 OTES 2 Rev. 1.1 ...
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Table of Contents 1. System Overview.................................................................................................... 21 1.1. CIP-51™ Microcontroller Core.......................................................................... 27 1.1.1. Fully 8051 Compatible.............................................................................. 27 1.1.2. Improved Throughput ............................................................................... 27 1.1.3. Additional Features .................................................................................. 27 1.2. On-Chip Memory............................................................................................... 29 1.3. Universal Serial Bus Controller ......................................................................... 31 1.4. Voltage ...
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C8051F340/1/2/3/4/5/6/7/8/9 9.2.7. Register Descriptions ............................................................................... 94 9.3. Interrupt Handler ............................................................................................... 96 9.3.1. MCU Interrupt Sources and Vectors ........................................................ 96 9.3.2. External Interrupts .................................................................................... 96 9.3.3. Interrupt Priorities ..................................................................................... 97 9.3.4. Interrupt Latency ...................................................................................... 97 9.3.5. Interrupt Register Descriptions................................................................. 98 9.4. ...
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Mode ................................................................................... 140 14. Oscillators ............................................................................................................. 145 14.1.Programmable Internal High-Frequency (H-F) Oscillator ............................... 146 14.1.1.Internal H-F Oscillator Suspend Mode ................................................... 146 14.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 147 14.2.1.Calibrating the Internal L-F Oscillator..................................................... 147 14.3.External Oscillator Drive Circuit...................................................................... 149 ...
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C8051F340/1/2/3/4/5/6/7/8/9 17.2.SMBus Configuration...................................................................................... 206 17.3.SMBus Operation ........................................................................................... 206 17.3.1.Arbitration............................................................................................... 207 17.3.2.Clock Low Extension.............................................................................. 208 17.3.3.SCL Low Timeout................................................................................... 208 17.3.4.SCL High (SMBus Free) Timeout .......................................................... 208 17.4.Using the SMBus............................................................................................ 208 17.4.1.SMBus Configuration Register............................................................... 210 17.4.2.SMB0CN Control Register ..................................................................... 213 17.4.3.Data Register ...
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Two 8-bit Counter/Timers (Timer 0 Only)................................. 258 21.2.Timer 2 .......................................................................................................... 263 21.2.1.16-bit Timer with Auto-Reload................................................................ 263 21.2.2.8-bit Timers with Auto-Reload................................................................ 264 21.2.3.Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge ...... 265 21.3.Timer 3 .......................................................................................................... 269 21.3.1.16-bit ...
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C8051F340/1/2/3/4/5/6/7/8 OTES 8 Rev. 1.1 ...
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... Figure 1.4. C8051F349 Block Diagram .................................................................... 26 Figure 1.5. On-Chip Clock and Reset ...................................................................... 28 Figure 1.6. On-Chip Memory Map for 64kB Devices (C8051F340/2/4/6) ................ 29 Figure 1.7. On-Chip Memory Map for 32 kB Devices (C8051F341/3/5/7/8/9) ......... 30 Figure 1.8. USB Block Diagram ............................................................................... 31 Figure 1.9. Digital Crossbar Diagram ....................................................................... 33 Figure 1.10. PCA Block Diagram.............................................................................. 34 Figure 1 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 Figure 9.1. CIP-51 Block Diagram............................................................................ 81 Figure 9.2. On-Chip Memory Map for 64 kB Devices (C8051F340/2/4/6) ............... 87 Figure 9.3. On-Chip Memory Map for 32 kB Devices (C8051F341/3/5/7/8/9) ......... 88 10. Prefetch Engine 11. Reset Sources Figure 11.1. Reset Sources.................................................................................... 111 Figure 11.2. Power-On and VDD Monitor Reset Timing ........................................ 112 12 ...
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C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 11 ...
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C8051F340/1/2/3/4/5/6/7/8/9 Figure 22.9. PCA 16-Bit PWM Mode...................................................................... 283 Figure 22.10. PCA Module 4 with Watchdog Timer Enabled ................................. 284 23. C2 Interface Figure 23.1. Typical C2 Pin Sharing....................................................................... 293 12 Rev. 1.1 ...
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N : OTES C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 13 ...
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C8051F340/1/2/3/4/5/6/7/8/9 14 Rev. 1.1 ...
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List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 22 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* .................................................................. 37 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics ....................................................... 38 Table 3.2. Index ...
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C8051F340/1/2/3/4/5/6/7/8/9 Table 17.3. Sources for Hardware Changes to SMB0CN ..................................... 215 Table 17.4. SMBus Status Decoding ..................................................................... 221 18. UART0 Table 18.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator ... 230 19. UART1 (C8051F340/1/4/5/8 Only) Table 19.1. ...
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List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 56 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 148 SFR Definition 14.4. OSCXCN: External Oscillator Control . . . . . ...
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USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte . . . 199 USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte . . . . . . . . . . . . . . ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 22.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 290 C2 Register Definition 23.1. C2ADD: C2 Address . . . . . . . . ...
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System Overview C8051F340/1/2/3/4/5/6/7/8/9 devices are fully integrated mixed-signal System-on-a-Chip MCUs. High- lighted features are listed below. Refer to Table 1.1 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core ( MIPS) • In-system, full-speed, non-intrusive ...
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... C8051F340/1/2/3/4/5/6/7/8/9 Table 1.1. Product Selection Guide C8051F340-GQ 48 64k 4352 C8051F341-GQ 48 32k 2304 C8051F342-GQ 48 64k 4352 C8051F343-GQ 48 32k 2304 C8051F344-GQ 25 64k 4352 C8051F345-GQ 25 32k 2304 C8051F346-GQ 25 64k 4352 C8051F347-GQ 25 32k 2304 C8051F348-GQ 25 32k 2304 C8051F349-GQ 25 32k 2304 — — Rev. 1.1 2 TQFP48 ...
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C2D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 64/32k Byte ISP FLASH Supply Program Memory Monitor VDD 256 Byte RAM Power Net Voltage VREG 4/2k Byte XRAM Regulator GND System Clock Setup XTAL1 External XTAL2 ...
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C8051F340/1/2/3/4/5/6/7/8/9 C2D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 64/32 kB ISP FLASH Supply Program Memory Monitor VDD 256 Byte RAM Power Net Voltage VREG 4/2 kB XRAM Regulator GND System Clock Setup XTAL1 External ...
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C2D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 32k Byte ISP FLASH Supply Program Memory Monitor VDD 256 Byte RAM Power Net Voltage VREG 2k Byte XRAM Regulator GND System Clock Setup XTAL1 External XTAL2 ...
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C8051F340/1/2/3/4/5/6/7/8/9 C2D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 32 kB ISP FLASH Supply Program Memory Monitor VDD 256 Byte RAM Power Net Voltage VREG 2 kB XRAM Regulator GND System Clock Setup XTAL1 External ...
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CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F340/1/2/3/4/5/6/7/8/9 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compil- ers can be used to develop software. ...
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C8051F340/1/2/3/4/5/6/7/8/9 Comparator 0 Px.x Px.x Internal LF Oscillator Internal HF Oscillator System Clock Clock Multiplier External XTAL1 Oscillator Clock Select XTAL2 Drive Figure 1.5. On-Chip Clock and Reset 28 VDD Supply Monitor Enable + - Power On Reset + - ...
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... On-chip XRAM is also included for the entire device family. The 64 k FLASH devices (C8051F340/2/4/6) have XRAM space. The 32 k Flash devices (C8051F341/3/5/7/8/9) have XRAM space. A separate 1 k Bytes of USB FIFO RAM is also included on all devices. See Figure 1.6 for the MCU system memory map of the 64k Flash devices ...
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... C8051F340/1/2/3/4/5/6/7/8/9 PROGRAM/DATA MEMORY (FLASH) 0x7FFF FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 Figure 1.7. On-Chip Memory Map for 32 kB Devices (C8051F341/3/5/7/8/9) 30 DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE 0xFF Upper 128 RAM (Indirect Addressing Only) (Direct Addressing Only) 0x80 0x7F (Direct and Indirect ...
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Universal Serial Bus Controller The Universal Serial Bus Controller (USB0 USB 2.0 compliant Full or Low Speed function with inte- grated transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional control ...
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C8051F340/1/2/3/4/5/6/7/8/9 1.4. Voltage Regulator C8051F340/1/2/3/4/5/6/7/8/9 devices include a voltage regulator (REG0). When enabled, the REG0 output appears on the V pin, and can also be used to power other external devices. REG0 can be enabled/dis- DD abled by software. 1.5. ...
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Programmable Digital I/O and Crossbar C8051F340/1/4/5/8 devices include 40 I/O pins (five byte-wide Ports); C8051F342/3/6/7/9 devices include 25 I/O pins (three byte-wide Ports, and a 1-bit-wide Port). The C8051F340/1/2/3/4/5/6/7/8/9 Ports behave like typical 8051 Ports with a few enhancements. ...
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C8051F340/1/2/3/4/5/6/7/8/9 1.7. Serial Ports The C8051F340/1/2/3/4/5/6/7/8/9 Family includes an SMBus/I2C interface, full-duplex UARTs, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little ...
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Analog to Digital Converter The C8051F340/1/2/3/4/5/6/7 devices include an on-chip 10-bit SAR ADC with a true differential input mul- tiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL of ±1LSB. ...
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C8051F340/1/2/3/4/5/6/7/8/9 1.10. Comparators C8051F340/1/2/3/4/5/6/7/8/9 devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port ...
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Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or /RST with respect to GND Voltage on V with respect to GND DD Maximum Total current through ...
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C8051F340/1/2/3/4/5/6/7/8/9 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter 1 Digital Supply Voltage Digital Supply RAM Data Retention Voltage 2 C8051F340/1/2/3 SYSCLK (System Clock) C8051F344/5/6/7/8/9 ...
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Table 3.1. Global DC Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter 3 Frequency Sensitivity º º ...
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C8051F340/1/2/3/4/5/6/7/8/9 Table 3.2. Index to Electrical Characteristics Tables Table Title ADC0 Electrical Characteristics Voltage Reference Electrical Characteristics Comparator Electrical Characteristics Voltage Regulator Electrical Specifications Reset Electrical Characteristics Flash Electrical Characteristics AC Parameters for External Memory Interface Oscillator Electrical Characteristics Port ...
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Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9 Pin Numbers Name 48-pin 32-pin Power In DD GND 7 3 /RST C2CK C2D C2D REGIN 11 ...
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C8051F340/1/2/3/4/5/6/7/8/9 Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9 (Continued) Pin Numbers Name 48-pin 32-pin P2.0 38 ...
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Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9 (Continued) Pin Numbers Name Type 48-pin 32-pin P3.6 24 ...
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C8051F340/1/2/3/4/5/6/7/8/9 P0.5 1 P0.4 2 P0.3 3 P0.2 4 P0.1 5 C8051F340/1/4/5/8 P0.0 6 GND VDD 10 REGIN 11 VBUS 12 Figure 4.1. TQFP-48 Pinout Diagram (Top View) 44 Top View Rev. 1.1 P2.2 36 ...
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C8051F340/1/2/3/4/5/6/7/8/9 Table 4.2. TQFP-48 Package Dimensions Dimension Min A — A1 0.05 A2 0.95 b 0. 0.45 aaa bbb ccc ddd θ 0° Notes: 1. All dimensions shown are in millimeters (mm) ...
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C8051F340/1/2/3/4/5/6/7/8/9 P0.1 1 P0.0 2 GND VDD 6 REGIN 7 VBUS 8 Figure 4.3. LQFP-32 Pinout Diagram (Top View) 46 C8051F342/3/6/7/9 Top View Rev. 1.1 P1 P1.3 P1.4 22 P1.5 21 P1.6 20 ...
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C8051F340/1/2/3/4/5/6/7/8/9 Table 4.3. LQFP-32 Package Dimensions Dimension Min A — A1 0.05 A2 1.35 b 0. 0.45 aaa bbb ccc ddd θ 0° Notes: 1. All dimensions shown are in millimeters (mm) ...
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C8051F340/1/2/3/4/5/6/7/8 OTES 48 Rev. 1.1 ...
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ADC (ADC0, C8051F340/1/2/3/4/5/6/7 Only) The ADC0 subsystem for the C8051F340/1/2/3/4/5/6/7/8/9 consists of two analog multiplexers (referred to collectively as AMUX0), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion ...
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C8051F340/1/2/3/4/5/6/7/8/9 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. The positive input (AIN+) can be connected to individual Port pins, the on-chip temperature sensor, or the positive power supply (V input (AIN-) can be connected ...
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Temperature Sensor The temperature sensor transfer function is shown in Figure 5.2. The output voltage (V ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. Values for the Offset and Slope parameters can be ...
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C8051F340/1/2/3/4/5/6/7/8/9 5.0 0 4.0 0 3.0 0 2.0 0 1.0 0 0.0 0 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2. 40.0 0.0 20 Temperature ...
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Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + ...
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C8051F340/1/2/3/4/5/6/7/8/9 5.3.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 ...
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Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0P4–0: AMUX0 Positive Input Selection AMX0P4-0 00000 00001 00010 00011 00100 00101 ...
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SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00000000 Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection. Note that ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 5.3. ADC0CF: ADC0 Configuration R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to ...
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SFR Definition 5.6. ADC0CN: ADC0 Control R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active ...
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C8051F340/1/2/3/4/5/6/7/8/9 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 conversion results to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space ...
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SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Low ...
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C8051F340/1/2/3/4/5/6/7/8/9 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF ...
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Window Detector In Differential Mode Figure 5.8 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF ...
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C8051F340/1/2/3/4/5/6/7/8/9 Table 5.1. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V, –40 to +85 °C unless otherwise specified DD Parameter Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic Performance (10 kHz ...
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Voltage Reference (C8051F340/1/2/3/4/5/6/7 Only) The Voltage reference MUX on C8051F340/1/2/3/4/5/6/7/8/9 devices is configurable to use an externally connected voltage reference, the on-chip reference voltage generator, or the power supply voltage V (see Figure 6.1). The REFSL bit in the ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 6.1. REF0CN: Reference Control R/W R/W R Bit7 Bit6 Bit5 Bits7–3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. ...
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Comparators C8051F340/1/2/3/4/5/6/7/8/9 devices include two on-chip programmable voltage Comparators. A block diagram of the comparators is shown in Figure 7.1, where “n” is the comparator number (0 or 1). The two Comparators operate identically with the following exceptions: (1) ...
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C8051F340/1/2/3/4/5/6/7/8/9 CPTnMX Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system clock; the asynchronous output ...
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CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 7.2. Comparator Hysteresis Plot Comparator hysteresis is programmed using Bits3-0 in the ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 7.1. CPT0CN: Comparator0 Control R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: ...
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SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection R/W R/W R/W - CMX0N2 CMX0N1 CMX0N0 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b, Write = don’t care. Bits6–4: CMX0N2–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection R/W R/W R CP0RIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 rising-edge interrupt disabled. 1: Comparator0 rising-edge ...
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SFR Definition 7.4. CPT1CN: Comparator1 Control R/W R R/W CP1EN CP1OUT CP1RIF Bit7 Bit6 Bit5 Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1–. 1: Voltage ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection R/W R/W R/W - CMX1N2 CMX1N1 CMX1N0 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b, Write = don’t care. Bits6–4: CMX1N2–CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin ...
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SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection R/W R/W R CP1RIE CP1FIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP1RIE: Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 rising-edge interrupt disabled. 1: Comparator1 rising-edge ...
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C8051F340/1/2/3/4/5/6/7/8/9 Table 7.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. Parameter CP0+ – CP0– = 100 mV Response Time: Mode 0, ...
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Voltage Regulator (REG0) C8051F340/1/2/3/4/5/6/7/8/9 devices include a voltage regulator (REG0). When enabled, the REG0 output appears on the V pin and can be used to power external devices. REG0 can be enabled/disabled by DD software using bit REGEN in ...
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C8051F340/1/2/3/4/5/6/7/8/9 VBUS From VBUS REGIN VDD Power Net Figure 8.1. REG0 Configuration: USB Bus-Powered VBUS From VBUS From 5 V REGIN Power Net VDD Power Net Figure 8.2. REG0 Configuration: USB Self-Powered 78 VBUS ...
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Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled Figure 8.4. REG0 Configuration: No USB Connection ower Net VBUS Sense VBUS VBUS SenseREGIN 3 V Out wer Net 5 V In3 V Out ltag e Reg u ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 8.1. REG0CN: Voltage Regulator Control R/W R R/W REGDIS VBSTAT VBPOL Bit7 Bit6 Bit5 Bit7: REGDIS: Voltage Regulator Disable. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. Bit6: VBSTAT: VBUS Signal Status. 0: VBUS signal currently absent ...
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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...
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C8051F340/1/2/3/4/5/6/7/8/9 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for 82 Rev. 1.1 ...
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MOVX Instruction and Program Memory In the CIP-51, the MOVX instruction serves three purposes: accessing on-chip XRAM, accessing off-chip data XRAM (only on C8051F340/1/4/5/8 devices), and accessing on-chip program Flash memory. The Flash access feature provides a mechanism for ...
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C8051F340/1/2/3/4/5/6/7/8/9 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ORL A, #data OR immediate to A ORL direct direct byte ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL ...
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Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic CLR C Clear Carry CLR bit Clear direct bit SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit ANL C, bit AND direct ...
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C8051F340/1/2/3/4/5/6/7/8/9 Notes on Registers, Operands and Addressing Modes Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first ...
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Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but ...
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... Programmable in 512 Byte Sectors) 0x0000 Figure 9.3. On-Chip Memory Map for 32 kB Devices (C8051F341/3/5/7/8/9) 9.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F340/1/2/3/4/5/6/7/8/9 implements 64k or 32k bytes of this program memory space as in-system, re-programmable Flash memory. Note that on the C8051F340/2/4/6 (64k version), addresses above 0xFBFF are reserved ...
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Data Memory The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or ...
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C8051F340/1/2/3/4/5/6/7/8/9 9.2.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in ...
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Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 ...
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C8051F340/1/2/3/4/5/6/7/8/9 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description P1MDIN 0xF2 Port 1 Input Mode Configuration P1MDOUT 0xA5 Port 1 Output Mode Configuration P1SKIP 0xD5 Port 1 ...
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Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description SBUF0 0x99 UART0 Data Buffer SCON0 0x98 UART0 Control SMB0CF 0xC1 SMBus Configuration SMB0CN 0xC0 SMBus Control SMB0DAT 0xC2 ...
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C8051F340/1/2/3/4/5/6/7/8/9 9.2.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic 94 Rev. 1.1 ...
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SFR Definition 9.4. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 9. Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7– Register. This register serves as a second accumulator for certain arithmetic operations. 9.3. Interrupt Handler The CIP-51 includes an extended interrupt ...
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IT0 IN0PL /INT0 Interrupt 1 0 Active low, edge sensitive 1 1 Active high, edge sensitive 0 0 Active low, level sensitive 0 1 Active high, level sensitive /INT0 and /INT1 are assigned to Port pins as defined in the ...
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C8051F340/1/2/3/4/5/6/7/8/9 Table 9.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 (/ 0x0003 INT0) Timer 0 Overflow 0x000B External Interrupt 1 (/ 0x0013 INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 ...
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SFR Definition 9.7. IE: Interrupt Enable R/W R/W R/W EA ESPI0 ET2 Bit7 Bit6 Bit5 Bit7: EA: Enable All Interrupts. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set- tings. 0: Disable all interrupt sources. 1: ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 9.8. IP: Interrupt Priority R/W R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of ...
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SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 R/W R/W R/W ET3 ECP1 ECP0 Bit7 Bit6 Bit5 Bit7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PT3 PCP1 PCP0 Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set ...
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SFR Definition 9.11. EIE2: Extended Interrupt Enable 2 R/W R/W R Bit7 Bit6 Bit5 Bits7–2: UNUSED. Read = 000000b. Write = don’t care. Bit1: ES1: Enable UART1 Interrupt. This bit sets the masking of the UART1 interrupt. ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 9.13. IT01CF: INT0/INT1 Configuration R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to SFR Definition 21.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: ...
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Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts, are ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 9.14. PCON: Power Control R/W R/W R/W GF5 GF4 GF3 Bit7 Bit6 Bit5 Bits7–2: GF5–GF0: General Purpose Flags 5–0. These are general purpose flags for use under software control. Bit1: STOP: Stop Mode Select. Setting this bit ...
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N : OTES C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 107 ...
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C8051F340/1/2/3/4/5/6/7/8/9 108 Rev. 1.1 ...
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Prefetch Engine The C8051F340/1/2/3/4/5/6/7/8/9 family of devices incorporate a 2-byte prefetch engine. Because the access time of the FLASH memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch engine is necessary for full-speed ...
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C8051F340/1/2/3/4/5/6/7/8 OTES 110 Rev. 1.1 ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...
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C8051F340/1/2/3/4/5/6/7/8/9 11.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until Power-On Reset delay (T RST PORDelay typically less than 0.3 ms. Figure 11.2. plots ...
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Power-Fail Reset / V DD When a power-down transition or power irregularity causes V monitor will drive the /RST pin low and hold the CIP- reset state (see Figure 11.2). When V returns to a level above ...
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C8051F340/1/2/3/4/5/6/7/8/9 11.3. External Reset The external /RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of ...
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Software Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol- lowing a software forced reset. The state of the /RST pin is unaffected by this reset. ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 11.2. RSTSRC: Reset Source R/W R R/W USBRSF FERROR C0RSEF Bit7 Bit6 Bit5 Bit7: USBRSF: USB Reset Flag 0: Read: Last reset was not a USB reset; Write: USB resets disabled. 1: Read: Last reset was a ...
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Table 11.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter I = 8.5 mA, V /RST Output Low Voltage OL /RST Input High Voltage /RST Input Low Voltage /RST Input Pull-Up Current /RST = 0 ...
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C8051F340/1/2/3/4/5/6/7/8 OTES 118 Rev. 1.1 ...
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Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX instruction. Once cleared to logic 0, a ...
Page 120
C8051F340/1/2/3/4/5/6/7/8/9 12.1.3. Flash Write Procedure Bytes in Flash memory can be written one byte at a time groups of two. The FLBWE bit in register PFE0CN (SFR Definition 10.1) controls whether a single byte or a block of ...
Page 121
... Table 12.1. Flash Electrical Characteristics Parameter C8051F340/2/4/6* Flash Size C8051F341/3/5/7/8/9 Endurance Erase Cycle Time 25 MHz System Clock Write Cycle Time 25 MHz System Clock *Note: 1024 bytes at location 0xFC00 to 0xFFFF are reserved. 12.2. Non-Volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time ...
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... Unlocked FLASH Pages Figure 12.1. Flash Program Memory Map and Security Byte 122 0xFC00 0xFBFF Locked when any 0xFBFE other FLASH pages are locked C8051F341/3/5/7/8/9 0xFA00 Unlocked FLASH Pages Access limit set according to the FLASH security lock byte 0x0000 Rev. 1.1 ...
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The level of FLASH security depends on the FLASH access method. The three FLASH access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 12.1. PSCTL: Program Store R/W Control R/W R/W R Bit7 Bit6 Bit5 Bits7–3: Unused: Read = 00000b. Write = don’t care. Bit2: Reserved. Read = 0b. Must Write = 0b. Bit1: PSEE: Program Store ...
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SFR Definition 12.3. FLSCL: Flash Scale R/W R/W R/W FOSE Reserved Reserved Bit7 Bit6 Bit5 Bits7: FOSE: Flash One-shot Enable This bit enables the Flash read one-shot. When the Flash one-shot disabled, the Flash sense amps are enabled for a ...
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C8051F340/1/2/3/4/5/6/7/8 OTES 126 Rev. 1.1 ...
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... External Data Memory Interface and On-Chip XRAM 4k Bytes (C8051F340/2/4/ Bytes (C8051F341/3/5/7/8/9) of RAM are included on-chip, and mapped into the external data memory space (XRAM). The 1k Bytes of USB FIFO space can also be mapped into XRAM address space for additional general-purpose data storage. Additionally, an External Memory Interface (EMIF) is available on the C8051F340/1/4/5/8 devices, which can be used to access off-chip data memories and memory-mapped devices connected to the GPIO ports ...
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C8051F340/1/2/3/4/5/6/7/8/9 13.2. Accessing USB FIFO Space The C8051F340/1/2/3/4/5/6/7/8/9 include 1k of RAM which functions as USB FIFO space. Figure 13.1 shows an expanded view of the FIFO space and user XRAM. FIFO space is normally accessed via USB FIFO registers; ...
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Configuring the External Memory Interface Configuring the External Memory Interface consists of five steps: 1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is most common), and skip the associated pins in ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 13.1. EMI0CN: External Memory Interface Control R/W R/W R/W PGSEL7 PGSEL6 PGSEL5 Bit7 Bit6 Bit5 Bits7–0: PGSEL[7:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address ...
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SFR Definition 13.2. EMI0CF: External Memory Configuration R/W R/W R/W - USBFAE - Bit7 Bit6 Bit5 Bit7: Unused. Read = 0b. Write = don’t care. Bit6: USBFAE: USB FIFO Access Enable. 0: USB FIFO RAM not available through MOVX instructions. ...
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C8051F340/1/2/3/4/5/6/7/8/9 13.5. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 13.5.1. Multiplexed Configuration In Multiplexed mode, the Data Bus ...
Page 133
Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-multiplexed Configuration is shown in Figure 13.3. See page 137 for more information about Non-multiplexed operation. A[15: ...
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C8051F340/1/2/3/4/5/6/7/8/9 13.6.1. Internal XRAM Only When EMI0CF.[3:2] are set to ‘00’, all MOVX instructions will target the internal XRAM space on the device. Memory accesses to addresses beyond the populated space will wrap boundaries (depending on ...
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Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space. • Effective addresses below the internal XRAM size boundary will access on-chip XRAM space. ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 13.3. EMI0TC: External Memory Timing Control R/W R/W R/W EAS1 EAS0 EWR3 Bit7 Bit6 Bit5 Bits7–6: EAS1–0: EMIF Address Setup Time Bits. 00: Address setup time = 0 SYSCLK cycles. 01: Address setup time = 1 SYSCLK ...
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Non-multiplexed Mode 13.7.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. ADDR[15:8] P2 ADDR[7:0] P3 DATA[7:0] P4 /WR P1.7 /RD P1.6 ADDR[15:8] P2 ADDR[7:0] P3 DATA[7:0] P4 /RD P1.6 /WR P1.7 Figure 13.5. Non-multiplexed 16-bit MOVX Timing C8051F340/1/2/3/4/5/6/7/8/9 Nonmuxed 16-bit ...
Page 138
C8051F340/1/2/3/4/5/6/7/8/9 13.7.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing 138 EMIF ADDRESS ( from EMIF ...
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MOVX with Bank Select: EMI0CF[4:2] = ‘110’. ADDR[15:8] P3 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P1.3 /WR P1.7 /RD P1.6 ADDR[15:8] P3 EMIF ADDRESS (8 LSBs) from AD[7: ...
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C8051F340/1/2/3/4/5/6/7/8/9 13.7.2. Multiplexed Mode 13.7.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. ADDR[15:8] P3 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P1.3 /WR P1.7 /RD P1.6 ADDR[15:8] P3 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ...
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MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P1.3 /WR P1.7 /RD P1.6 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ...
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C8051F340/1/2/3/4/5/6/7/8/9 13.7.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. ADDR[15:8] P3 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P1.3 /WR P1.7 /RD P1.6 ADDR[15:8] P3 EMIF ADDRESS (8 LSBs) from AD[7: ...
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Table 13.1. AC Parameters for External Memory Interface Parameter Description T Address / Control Setup Time ACS T Address / Control Pulse Width ACW T Address / Control Hold Time ACH T Address Latch Enable High Time ALEH T Address ...
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C8051F340/1/2/3/4/5/6/7/8 OTES 144 Rev. 1.1 ...
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Oscillators C8051F340/1/2/3/4/5/6/7/8/9 devices include a programmable internal high-frequency oscillator, a pro- grammable internal low-frequency oscillator (C8051F340/1/2/3/4/5/8/9), an external oscillator drive circuit, and a 4x Clock Multiplier. The internal high-frequency and low-frequency oscillators can be enabled/dis- abled and adjusted using ...
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C8051F340/1/2/3/4/5/6/7/8/9 14.1. Programmable Internal High-Frequency (H-F) Oscillator All C8051F340/1/2/3/4/5/6/7/8/9 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be programmed via the OSCICL regis- ter shown in SFR ...
Page 147
SFR Definition 14.2. OSCICL: Internal H-F Oscillator Calibration R/W R/W R Bit7 Bit6 Bit5 Bits4–0: OSCCAL: Oscillator Calibration Value These bits determine the internal H-F oscillator period. When set to 00000b, the oscillator operates at its fastest ...
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C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control R/W R R/W OSCLEN OSCLRDY OSCLF3 Bit7 Bit6 Bit5 Bit7: OSCLEN: Internal L-F Oscillator Enable. 0: Internal L-F Oscillator Disabled. 1: Internal L-F Oscillator Enabled. Bit6: OSCLRDY: Internal L-F Oscillator Ready ...
Page 149
External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/ resonator must ...
Page 150
C8051F340/1/2/3/4/5/6/7/8/9 14.3.3. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 2. The capacitor should be no greater than 100 pF; ...
Page 151
SFR Definition 14.4. OSCXCN: External Oscillator Control R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal ...
Page 152
C8051F340/1/2/3/4/5/6/7/8/9 14.4. 4x Clock Multiplier The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full Speed USB communication (see Section “16.4. USB Clock Configuration” on page 182 the Multiplier output can also ...
Page 153
System and USB Clock Selection The internal oscillator requires little start-up time and may be selected as the system or USB clock immedi- ately following the OSCICN write that enables the internal oscillator. External crystals and ceramic resona- tors ...
Page 154
C8051F340/1/2/3/4/5/6/7/8/9 Internal Oscillator Clock Signal Input Source Selection USB Clock External Oscillator / 4 Crystal Oscillator Mode External Oscillator 24 MHz Crystal SFR Definition 14.6. CLKSEL: Clock Select R/W R/W R/W - USBCLK Bit7 Bit6 Bit5 Bit 7: Unused. Read ...
Page 155
Table 14.1. Oscillator Electrical Characteristics V = 2.7 to 3.6 V; –40 to +85 °C unless otherwise specified DD Parameter Internal High-Frequency Oscillator (Using Factory-Calibrated Settings) Oscillator Frequency IFCN = 11b Oscillator Supply Current 24 ºC, V (from V ) ...
Page 156
C8051F340/1/2/3/4/5/6/7/8 OTES 156 Rev. 1.1 ...
Page 157
Port Input/Output Digital and analog resources are available through 40 I/O pins (C8051F340/1/4/5/ I/O pins (C8051F342/3/6/7/9). Port pins are organized as shown in Figure 15.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) ...
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C8051F340/1/2/3/4/5/6/7/8/9 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT ANALOG INPUT PORT-INPUT Figure 15.2. Port I/O Cell Block Diagram 158 VDD GND Analog Select Rev. 1.1 VDD (WEAK) PORT PAD ...
Page 159
Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 15.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding ...
Page 160
C8051F340/1/2/3/4/5/6/7/8 Signals (32-pin Package) SF Signals (48-pin Package) PIN I TX0 RX0 SCK MISO MOSI NSS* *NSS is only pinned out in 4-wire SPI mode SDA SCL CP0 CP0A CP1 ...
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P0 SF Signals (32-pin Package) SF Signals (48-pin Package) PIN I TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 ...
Page 162
C8051F340/1/2/3/4/5/6/7/8/9 Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register ...
Page 163
SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W CP1AE CP1E CP0AE Bit7 Bit6 Bit5 Bit7: CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. Bit6: CP1E: ...
Page 164
C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 15.2. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W WEAKPUD XBARE T1E Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input ...
Page 165
General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports 3-0 are accessed through corresponding special function registers (SFRs) that are both ...
Page 166
C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 15.6. P0MDOUT: Port0 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding ...
Page 167
SFR Definition 15.8. P1: Port1 Latch R/W R/W R/W P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits7–0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’). 0: Logic Low Output. 1: Logic High Output (high ...
Page 168
C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 15.11. P1SKIP: Port1 Skip R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ...
Page 169
SFR Definition 15.14. P2MDOUT: Port2 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P2.7–P2.0 (respectively): ignored if corresponding bit in regis- ter P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n ...
Page 170
C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 15.16. P3: Port3 Latch R/W R/W R/W P3.7 P3.6 P3.5 Bit7 Bit6 Bit5 Bits7–0: P3.[7:0] Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = ...
Page 171
SFR Definition 15.19. P3SKIP: Port3 Skip R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: P3SKIP[3:0]: Port3 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC ...
Page 172
C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 15.21. P4MDIN: Port4 Input Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Analog Input Configuration Bits for P4.7–P4.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding ...
Page 173
Table 15.1. Port I/O DC Electrical Characteristics V = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified DD Parameters I = –3 mA, Port I/O push-pull –10 µA, Port I/O push-pull Output High Voltage ...
Page 174
C8051F340/1/2/3/4/5/6/7/8/9 174 Rev. 1.1 ...
Page 175
Universal Serial Bus Controller (USB0) C8051F340/1/2/3/4/5/6/7/8/9 devices include a complete Full/Low Speed USB function for USB peripheral implementations*. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), ...
Page 176
C8051F340/1/2/3/4/5/6/7/8/9 16.1. Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 16.1. Endpoint Addressing Scheme ...
Page 177
SFR Definition 16.1. USB0XCN: USB0 Transceiver Control R/W R/W R/W PREN PHYEN SPEED PHYTST1 PHYTST0 DFREC Bit7 Bit6 Bit5 Bit7: PREN: Internal Pull-up Resistor Enable The location of the pull-up resistor (D+ or D–) is determined by the SPEED bit. ...
Page 178
C8051F340/1/2/3/4/5/6/7/8/9 16.3. USB Register Access The USB0 controller registers listed in Table 16.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. ...
Page 179
SFR Definition 16.2. USB0ADR: USB0 Indirect Address R/W R/W R/W BUSY AUTORD Bit7 Bit6 Bit5 Bits7: BUSY: USB0 Register Read Busy Flag This bit is used during indirect USB0 register accesses. Software should write ‘1’ to this bit to initiate ...
Page 180
C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 16.3. USB0DAT: USB0 Data R/W R/W R/W Bit7 Bit6 Bit5 This SFR is used to indirectly read and write USB0 registers. Write Procedure: 1. Poll for BUSY (USB 0ADR.7) => ‘0’. 2. Load the target USB0 register ...
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Table 16.2. USB0 Controller Registers USB Register USB Register Name Address IN1INT 0x02 OUT1INT 0x04 CMINT 0x06 IN1IE 0x07 OUT1IE 0x09 CMIE 0x0B FADDR 0x00 POWER 0x01 FRAMEL 0x0C FRAMEH 0x0D INDEX 0x0E CLKREC 0x0F FIFOn 0x20–0x23 E0CSR 0x11 EINCSRL ...
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C8051F340/1/2/3/4/5/6/7/8/9 16.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must ...
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FIFO Management 1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between Endpoints0-3 as shown in Figure 16.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT, or both (Split ...
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C8051F340/1/2/3/4/5/6/7/8/9 16.5.2. FIFO Double Buffering FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. ...
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Function Addressing The FADDR register holds the current USB0 function address. Software should write the host-assigned 7-bit function address to the FADDR register when received as part of a SET_ADDRESS command. A new address written to FADDR will not ...
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C8051F340/1/2/3/4/5/6/7/8/9 “14. Oscillators” on page 145 for more details on internal oscillator configuration, including the Suspend mode feature of the internal oscillator. USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or gener- ated, ...
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USB Register Definition 16.8. POWER: USB0 Power R/W R/W R/W ISOUD - - USBINH Bit7 Bit6 Bit5 Bit7: ISOUD: ISO Update This bit affects all IN Isochronous endpoints. 0: When software writes INPRDY = ‘1’, USB0 will send the packet ...
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C8051F340/1/2/3/4/5/6/7/8/9 USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low Bit7 Bit6 Bit5 Bits7-0: Frame Number Low This register contains bits7-0 of the last received frame number. USB Register Definition 16.10. FRAMEH: USB0 Frame Number High R ...
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USB Register Definition 16.11. IN1INT: USB0 IN Endpoint Interrupt Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3: IN Endpoint 3 Interrupt-pending Flag This bit is cleared when software ...
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C8051F340/1/2/3/4/5/6/7/8/9 USB Register Definition 16.13. CMINT: USB0 Common Interrupt Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b; Write = don’t care. Bit3: SOF: Start of Frame Interrupt Set by hardware when a SOF token ...
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USB Register Definition 16.14. IN1IE: USB0 IN Endpoint Interrupt Enable R/W R/W R Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3E: IN Endpoint 3 Interrupt Enable 0: IN Endpoint 3 interrupt ...
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C8051F340/1/2/3/4/5/6/7/8/9 USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable 16.9. The Serial Interface Engine The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor when data has successfully been transmitted or received. When receiving ...
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The E0CNT register (USB Register Definition 16.18) holds the number of received data bytes in the Endpoint0 FIFO. Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may force a STALL condition to abort the ...
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C8051F340/1/2/3/4/5/6/7/8/9 16.10.3.Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware ...
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USB Register Definition 16.17. E0CSR: USB0 Endpoint0 Control R/W R/W R/W SSUEND SOPRDY SDSTL SUEND DATAEND Bit7 Bit6 Bit5 Bit7: SSUEND: Serviced Setup End Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event. ...
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C8051F340/1/2/3/4/5/6/7/8/9 USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count Bit7 Bit6 Bit5 Bit7: Unused. Read = 0; Write = don’t care. Bits6–0: E0CNT: Endpoint 0 Data Count This 7-bit number indicates the number of ...
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Writing ‘1’ to INPRDY without writing any data to the endpoint FIFO will cause a zero-length packet to be transmitted upon reception of the next IN token. A Bulk or Interrupt pipe can be shut down (or Halted) by writing ...
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C8051F340/1/2/3/4/5/6/7/8/9 USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low Byte R W R/W - CLRDT STSTL Bit7 Bit6 Bit5 Bit7: Unused. Read = 0; Write = don’t care. Bit6: CLRDT: Clear Data Toggle. Write: Software should write ‘1’ ...
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USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte R/W R/W R/W DBIEN ISO DIRSEL Bit7 Bit6 Bit5 Bit7: DBIEN: IN Endpoint Double-buffer Enable. 0: Double-buffering disabled for the selected IN endpoint. 1: Double-buffering enabled for the selected ...
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C8051F340/1/2/3/4/5/6/7/8/9 A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While SDSTL = ‘1’, hardware will respond to all OUT requests with a STALL condition. Each time hardware gen- erates ...