C8051F341-GQ Silicon Laboratories Inc, C8051F341-GQ Datasheet - Page 113

• Manufacturer Part Number: C8051F341-GQ
• Description: IC 8051 MCU FLASH 32K 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F34xr

Specifications of C8051F341-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 20x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SMBus/SPI/UART/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F340DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 17-ch x 10-bit
• No. Of I/o's: 40
• Ram Memory Size: 2304Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Data Rom Size: 128 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 17
• Height: 1 mm
• Length: 7 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1452 - ADAPTER PROGRAM TOOLSTICK F340
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1299

11.2. Power-Fail Reset / V
When a power-down transition or power irregularity causes V
monitor will drive the /RST pin low and hold the CIP-51 in a reset state (see Figure 11.2). When V
returns to a level above V
nal data memory contents are not altered by the power-fail reset, it is impossible to determine if V
dropped below the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be
valid. The V
not altered by any other reset source. For example, if the V
performed, the V
Important Note: The V
V
for configuring the V
See Figure 11.2 for V
monitor.
DD
Bit7:
Bit6:
Bits5–0: Reserved. Read = Variable. Write = don’t care.
VDMEN
monitor as a reset source before it is enabled and stabilized will cause a system reset. The procedure
R/W
Bit7
Step 1. Enable the V
Step 2. Wait for the V
Step 3. Select the V
VDMEN: V
This bit turns the V
until it is also selected as a reset source in register RSTSRC (SFR Definition 11.2). The V
Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
V
See Table 11.1 for the minimum V
lowing all POR resets.
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
DD
DD
DD
VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved
monitor is enabled after power-on resets; however its defined state (enabled/disabled) is
DD
DD
DD
DD
STAT: V
DD
monitor as a reset source before it has stabilized will generate a system reset.
Bit6
R
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
monitor will still be enabled after the reset.
DD
SFR Definition 11.1. VDM0CN: V
DD
DD
monitor as a reset source is shown below:
DD
DD
monitor timing. See Table 11.1 for complete electrical characteristics of the V
RST
Monitor Enable.
monitor must be enabled before it is selected as a reset source. Selecting the
Status.
DD
, the CIP-51 will be released from the reset state. Note that even though inter-
Bit5
DD
R
DD
DD
monitor as a reset source (RSTSRC.1 = ‘1’).
monitor (VDM0CN.7 = ‘1’).
monitor to stabilize (see Table 11.1 for the V
DD
monitor circuit on/off. The V
DD
monitor threshold.
Monitor
DD
Bit4
R
monitor threshold.
DD
C8051F340/1/2/3/4/5/6/7/8/9
Rev. 1.1
Monitor turn-on time. The V
Bit3
R
DD
DD
DD
Bit2
DD
monitor is enabled and a software reset is
R
DD
Monitor cannot generate system resets
Monitor Control
to drop below V
Monitor output).
Bit1
R
DD
DD
Monitor is enabled fol-
Monitor turn-on time).
RST
Bit0
R
, the power supply
SFR Address:
Reset Value
Variable
0xFF
DD
113
DD
DD
DD