C8051F341-GQ Silicon Laboratories Inc, C8051F341-GQ Datasheet - Page 10

• Manufacturer Part Number: C8051F341-GQ
• Description: IC 8051 MCU FLASH 32K 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F34xr

Specifications of C8051F341-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 20x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SMBus/SPI/UART/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F340DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 17-ch x 10-bit
• No. Of I/o's: 40
• Ram Memory Size: 2304Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Data Rom Size: 128 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 17
• Height: 1 mm
• Length: 7 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1452 - ADAPTER PROGRAM TOOLSTICK F340
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1299

C8051F340/1/2/3/4/5/6/7/8/9
10. Prefetch Engine
11. Reset Sources
12. Flash Memory
13. External Data Memory Interface and On-Chip XRAM
14. Oscillators
15. Port Input/Output
16. Universal Serial Bus Controller (USB0)
17. SMBus
18. UART0
10
Figure 9.1. CIP-51 Block Diagram............................................................................ 81
Figure 9.2. On-Chip Memory Map for 64 kB Devices (C8051F340/2/4/6) ............... 87
Figure 9.3. On-Chip Memory Map for 32 kB Devices (C8051F341/3/5/7/8/9) ......... 88
Figure 11.1. Reset Sources.................................................................................... 111
Figure 11.2. Power-On and VDD Monitor Reset Timing ........................................ 112
Figure 12.1. Flash Program Memory Map and Security Byte................................. 122
Figure 13.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’ .. 128
Figure 13.2. Multiplexed Configuration Example.................................................... 132
Figure 13.3. Non-multiplexed Configuration Example ............................................ 133
Figure 13.4. EMIF Operating Modes ...................................................................... 133
Figure 13.5. Non-multiplexed 16-bit MOVX Timing ................................................ 137
Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 138
Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 139
Figure 13.8. Multiplexed 16-bit MOVX Timing........................................................ 140
Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing ......................... 141
Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing ............................ 142
Figure 14.1. Oscillator Diagram.............................................................................. 145
Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ................ 157
Figure 15.2. Port I/O Cell Block Diagram ............................................................... 158
Figure 15.3. Peripheral Availability on Port I/O Pins............................................... 159
Figure 15.4. Crossbar Priority Decoder in Example Configuration
Figure 15.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped) ...
Figure 16.1. USB0 Block Diagram.......................................................................... 175
Figure 16.2. USB0 Register Access Scheme......................................................... 178
Figure 16.3. USB FIFO Allocation .......................................................................... 183
Figure 17.1. SMBus Block Diagram ....................................................................... 205
Figure 17.2. Typical SMBus Configuration ............................................................. 206
Figure 17.3. SMBus Transaction ............................................................................ 207
Figure 17.4. Typical SMBus SCL Generation......................................................... 211
Figure 17.5. Typical Master Transmitter Sequence................................................ 217
Figure 17.6. Typical Master Receiver Sequence.................................................... 218
Figure 17.7. Typical Slave Receiver Sequence...................................................... 219
Figure 17.8. Typical Slave Transmitter Sequence.................................................. 220
Figure 18.1. UART0 Block Diagram ....................................................................... 223
(No Pins Skipped)160
161
Rev. 1.1