M38507F8AFP#U1 Renesas Electronics America, M38507F8AFP#U1 Datasheet
M38507F8AFP#U1
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M38507F8AFP#U1 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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Group (Spec.A QzROM version) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3850 group (spec.A QzROM version) is the 8-bit microcomputer based on the 740 family core technology. The 3850 group (spec.A QzROM version) is designed for the household products and ...
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Group (Spec.A QzROM version) Fig 2. Functional block diagram Rev.2.13 Apr 17, 2009 Page REJ03B0125-0213 ...
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Group (Spec.A QzROM version) PIN DESCRIPTION Table 1 Pin description Pin Name Power source CC SS CNV CNV input Reference REF voltage AV Analog power SS source RESET Reset input X Clock input ...
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Group (Spec.A QzROM version) PART NUMBERING Product name M3850 Fig 3. Part numbering Rev.2.13 Apr 17, 2009 Page REJ03B0125-0213 A- XXX SP Package type SP : PRDP0042BA PRSP0042GA-A/B ROM number Omitted ...
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Group (Spec.A QzROM version) GROUP EXPANSION Renesas Technology expands the 3850 group (spec.A QzROM version) as follows. Memory Type Support for QzROM version. Memory Expansion ROM size (bytes) ROM external 32K 28K 24K 20K 16K 12K 8K Fig 4. ...
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Group (Spec.A QzROM version) GROUP DESCRIPTION The QzROM version, mask ROM version and the flash memory version of 3850 group (Spec.A) are mass production. Currently support products are listed below. Table 3 Support products (mask ROM version and flash ...
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Group (Spec.A QzROM version) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3850 group (spec.A) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual ...
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Group (Spec.A QzROM version) Interrupt request Push return M(S)←( address on stack (S)←(S) − 1 M(S)←( ← − Subroutine Execute RTS (S)←( POP return address from ...
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Group (Spec.A QzROM version) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch ...
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Group (Spec.A QzROM version) [CPU Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit, the internal system clock control bits, etc. The CPU mode register is allocated at address 003B b7 Fig 7. Structure ...
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Group (Spec.A QzROM version) MEMORY • Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. • RAM RAM is used for data storage and for ...
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Group (Spec.A QzROM version) 0000 Port P0 (P0) 16 0001 Port P0 direction register (P0D) 16 0002 Port P1 (P1) 16 0003 Port P1 direction register (P1D) 16 0004 Port P2 (P2) 16 0005 Port P2 direction register (P2D) ...
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Group (Spec.A QzROM version) I/O PORTS The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be ...
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Group (Spec.A QzROM version) (1) Port P0 0 Pull-up control bit Direction register Data bus Port latch Serial I/O2 input (3) Port P0 2 Pull-up control bit P0 /S P-channel output disable bit CLK2 2 Serial I/O2 synchronous clock ...
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Group (Spec.A QzROM version) (9) Port P2 4 Pull-up control bit Serial I/O1 enable bit Receive enable bit Direction register Data bus Port latch Serial I/O1 input (11) Port P2 6 Pull-up control bit Serial I/O1 synchronous clock selection ...
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Group (Spec.A QzROM version) (17) Port P4 Fig 12. Port block diagram (3) Rev.2.13 Apr 17, 2009 Page REJ03B0125-0213 4 Pull-up control bit PWM function enable bit Direction register Data bus Port latch PWM output Interrupt ...
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Group (Spec.A QzROM version Fig 13. Structure of port registers (1) Rev.2.13 Apr 17, 2009 Page REJ03B0125-0213 Port P0, P1, P2 pull-up control register (PULL012: address 0012 ) 16 P0 pull-up control ...
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Group (Spec.A QzROM version Fig 14. Structure of port registers (2) Rev.2.13 Apr 17, 2009 Page REJ03B0125-0213 Port P4 pull-up control register (PULL4 : address 0014 ) 16 P4 pull-up control bit 0 0: ...
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Group (Spec.A QzROM version) INTERRUPTS Interrupts occur by 15 sources among 15 sources: six external, eight internal, and one software. • Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt ...
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Group (Spec.A QzROM version) Table 8 Interrupt vector addresses and priority Addresses Interrupt Source Priority High (2) 1 FFFD Reset INT 2 FFFB 0 Reserved 3 FFF9 INT 4 FFF7 1 INT 5 FFF5 2 INT /Serial I/O2 6 ...
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Group (Spec.A QzROM version) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) Fig 15. Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A INT interrupt edge selection bit 0 INT interrupt edge selection bit ...
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Group (Spec.A QzROM version) TIMERS The 3850 group (spec.A) has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the ...
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Group (Spec.A QzROM version) f(X )/16 IN (f(X )/16 at low-speed mode) CIN f(X )/2 IN (f(X )/2 at low-speed mode) CIN Timer X count source selection bit CNTR active edge 0 selection bit P2 /CNTR 7 0 “0” ...
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Group (Spec.A QzROM version) SERIAL INTERFACE • Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O1. A dedicated timer is also provided for baud rate generation ...
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Group (Spec.A QzROM version) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data ...
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Group (Spec.A QzROM version) Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 ST Serial output TXD Receive buffer read signal ST Serial input RXD Notes 1: Error flag detection occurs at the same time that the ...
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Group (Spec.A QzROM version) Serial I/O1 status register b7 b0 (SIOSTS : address 0019 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion ...
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Group (Spec.A QzROM version) • Serial I/O2 The serial I/O2 can be operated only as the clock synchronous type synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 ...
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Group (Spec.A QzROM version) X CIN “10” Main clock division ratio selection bits (Note) “00” X “01” latch 3 “0” RDY2 S “1” S output enable bit RDY2 Serial I/O2 P0 synchronous clock selection ...
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Group (Spec.A QzROM version) S CMP2 S CLK2 S OUT2 S IN2 Fig 28. S output operation CMP2 Rev.2.13 Apr 17, 2009 Page REJ03B0125-0213 Judgment of I/O data comparison ...
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Group (Spec.A QzROM version) PWM (PWM: Pulse Width Modulation) The 3850 group (spec.A) has a PWM function with an 8-bit resolution, based on a signal that is the clock input X clock input divided by 2. • Data Setting ...
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Group (Spec.A QzROM version) b7 Fig 31. Structure of PWM control register PWM output PWM register write signal PWM prescaler write signal When the contents of the PWM register or PWM prescaler have changed, the PWM output will change ...
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Group (Spec.A QzROM version) A/D CONVERTER [AD Conversion Registers (ADL, ADH)] 0035 The AD conversion registers are read-only registers that store the result of an A/D conversion. Do not read these registers during an A/D conversion. [AD Control Register ...
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Group (Spec.A QzROM version control register (Address 0034 ) / / / Comparator ...
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Group (Spec.A QzROM version) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of ...
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Group (Spec.A QzROM version) RESET CIRCUIT To reset the microcomputer, RESET pin must be held at an “L” level for 20 cycles or more Then the RESET pin is IN returned to an “H” level (the ...
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Group (Spec.A QzROM version) (1) Port P0 (P0) (2) Port P0 direction register (P0D) (3) Port P1 (P1) Port P1 direction register (P1D) (4) (5) Port P2 (P2) (6) Port P2 direction register (P2D) (7) Port P3 (P3) (8) ...
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Group (Spec.A QzROM version) CLOCK GENERATING CIRCUIT The 3850 group (spec. A QzROM version) has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between Use the circuit constants in accordance ...
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Group (Spec.A QzROM version) [MISRG (MISRG)] 0038 16 MISRG consists of three control bits (bits for middle- speed mode automatic switch and one control bit (bit 0) for oscillation stabilizing time set after STP instruction released. ...
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Group (Spec.A QzROM version) Reset Middle-speed mode CM 6 (f(φ MHz) “1”←→”0” MHz oscillating (32 kHz stopped) 4 Middle-speed mode CM 6 (f(φ ...
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Group (Spec.A QzROM version) ELECTRICAL CHARACTERISTICS Absolute maximum ratings Table 9 Absolute maximum ratings Symbol Parameter V Power source voltage CC V Input voltage REF V Input voltage ...
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Group (Spec.A QzROM version) Recommended operating conditions Table 10 Recommended operating conditions (1) (V Symbol Parameter V (1) Power source voltage CC V Power source voltage SS V “H” input voltage ...
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Group (Spec.A QzROM version) Table 11 Recommended operating conditions (2) (V Symbol I (1) “H” peak output current OH(peak) I (1) “L” peak output current OL(peak) I (1) “L” peak output current OL(peak) I “H” average output current OH(avg) ...
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Group (Spec.A QzROM version) Electrical characteristics Table 12 Electrical characteristics (1) (V Symbol Parameter V (1) “H” output voltage ...
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Group (Spec.A QzROM version) Table 13 Electrical characteristics (2) (V Symbol Parameter I Power source High-speed mode CC current Middle-speed mode Low-speed mode ( Low-speed mode ( Increment when A/D conversion ...
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Group (Spec.A QzROM version) A/D converter recommended operating conditions Table 14 A/D converter recommended operating conditions (V = 2 Symbol Parameter V Power source voltage CC (When A/D converter is used) V A/D ...
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Group (Spec.A QzROM version) Timing Requirements Table 16 Timing requirements (1) (V Symbol t (RESET) Reset input “L” pulse width External clock input cycle time External clock input “H” pulse ...
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Group (Spec.A QzROM version) Switching characteristics Table 18 Switching characteristics (1) (V Symbol Parameter CLK1 Serial I/O1 clock output “H” pulse width CLK1 Serial I/O1 clock output “L” pulse width t ...
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Group (Spec.A QzROM version) CNTR 0 CNTR 1 INT to INT 0 3 RESET CLK1 S CLK2 IN2 OUT2 Fig 48. Timing diagram Rev.2.13 Apr 17, 2009 Page ...
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Group (Spec.A QzROM version) PACKAGE OUTLINE Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. JEITA Package Code RENESAS Code P-SDIP42-13x36.72-1.78 PRDP0042BA SEATING PLANE ...
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Group (Spec.A QzROM version) APPENDIX NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular essential to initialize the T and ...
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Group (Spec.A QzROM version) NOTES ON PERIPHERAL FUNCTIONS Notes on Input and Output Ports 1. Notes in standby state *1 In standby state , do not make input levels of an I/O port “undefined”, especially for I/O ports of ...
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Group (Spec.A QzROM version) Notes on Interrupts 1. Change of relevant register settings When the setting of the following registers or bits is changed, the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence ...
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Group (Spec.A QzROM version) 2. Notes when selecting clock asynchronous serial I/O (Serial I/O1) (1) Stop of transmission operation Clear the transmit enable bit to “0” (transmit disabled). <Reason> Since transmission is not stopped and the transmission circuit is ...
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Group (Spec.A QzROM version) Notes on A/D Converter 1. Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 Further, be sure to verify the ...
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Group (Spec.A QzROM version) Handling of Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (V pin) and GND pin ( source pin ...
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REVISION HISTORY REVISION HISTORY Rev. Date Page − 1.00 Dec. 10, 2004 1 5 − 2.00 Sep. 09, 2005 1, 4 2.01 Oct. 13, 2005 5 11 ...
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REVISION HISTORY Rev. Date Page 2.11 Dec. 19, 2008 38 41- − 2.13 Apr. 17, 2009 All trademarks and registered trademarks are the property of their respective owners. 3850 Group (Spec.A QzROM version) Data Sheet ...
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...