M38507F8AFP#U1 Renesas Electronics America, M38507F8AFP#U1 Datasheet - Page 40

• Manufacturer Part Number: M38507F8AFP#U1
• Description: IC 740/3850 MCU FLASH 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38507F8AFP#U1

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 12.5 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: UART
• On-chip Adc: 9-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3850 Group (Spec.A QzROM version)
Rev.2.13
REJ03B0125-0213
CLOCK GENERATING CIRCUIT
The 3850 group (spec. A QzROM version) has two built-in
oscillation circuits. An oscillation circuit can be formed by
connecting a resonator between X
X
resonator manufacturer’s recommended values. No external
resistor is needed between X
resistor exists on-chip.(An external feed-back resistor may be
needed depending on conditions.) However, an external feed-
back resistor is needed between X
Immediately after power on, only the X
starts oscillating, and X
• Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of X
reset is released, this mode is selected.
(2) High-speed mode
The internal clock φ is half the frequency of X
(3) Low-speed mode
The internal clock φ is half the frequency of X
(4) Low power dissipation mode
The low power consumption operation can be realized by
stopping the main clock X
main clock, set bit 5 of the CPU mode register to “1”. When the
main clock X
“0”), set sufficient time for oscillation to stabilize.
The sub-clock X
input clocks that are generated externally. Accordingly, make
sure to cause an external resonator to oscillate.
<Note>
The internal reset may not be generated correctly in the middle-
speed mode, depending on the underflow timing of the watchdog
timer.
When using the watchdog timer, operate the MCU in any mode
other than the middle-speed mode.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and X
oscillation stabilizing time set after STP instruction released bit
(bit 0 of address 0038
and timer 1 is set to “01
set after STP instruction released bit is “1”, set the sufficient time
for oscillation of used oscillator to stabilize since nothing is set to
the prescaler 12 and timer 1.
After STP instruction is released, the input of the prescaler 12 is
connected to count source which had set at executing the STP
instruction, and the output of the prescaler 12 is connected to
timer 1. Oscillator restarts when an external interrupt is received,
but the internal clock φ is not supplied to the CPU (remains at
“H”) until timer 1 underflows. The internal clock φ is supplied
for the first time, when timer 1 underflows. This ensures time for
the clock oscillation using the ceramic resonators to be
stabilized. When the oscillator is restarted by reset, apply “L”
level to the RESET pin until the oscillation is stable since a wait
time will not be generated.
COUT
). Use the circuit constants in accordance with the
IN
Apr 17, 2009
is restarted (by setting the main clock stop bit to
CIN
IN
-X
16
and X
CIN
COUT
16
) is “0”, the prescaler 12 is set to “FF
”. When the oscillation stabilizing time
and X
IN
CIN
oscillating circuit can not directly
in low-speed mode. To stop the
IN
COUT
Page 38 of 56
CIN
oscillation stops. When the
and X
and X
IN
pins function as I/O ports.
OUT
and X
IN
IN
COUT
divided by 8. After
oscillation circuit
since a feed-back
IN
CIN
OUT
.
.
.
(X
CIN
and
16
”
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ
restarts at reset or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
To ensure that the interrupts will be received to release the STP
or WIT state, their interrupt enable bits must be set to “1” before
executing of the STP or WIT instruction.
When releasing the STP state,
timer 1 is connected to the count source which had set at
executing the STP instruction and the prescaler 12 and
timer 1 will start counting. Set the timer 1 interrupt enable
bit to
<Notes>
• If you switch the mode between middle/high-speed and low-
• When using the oscillation stabilizing time set after STP
Fig 42. Ceramic resonator circuit
Fig 43. External clock input circuit
speed, stabilize both X
time is required for the sub-clock to stabilize, especially
immediately after power on and at returning from the stop
mode. When switching the mode between middle/high-speed
and low-speed, set the frequency on condition that f(X
f(X
instruction released bit set to “1”, evaluate time to stabilize
oscillation of the used oscillator and set the value to the timer 1
and prescaler 12.
CIN
Notes : Insert a damping resistor if required.
“0”
).
before executing the STP instruction.
X
The resistance will vary depending on the oscillator and
the oscillation drive capacity setting.
Use the value recommended by the maker of the
oscillator.
Also, if the oscillator manufacturer's data sheet specifies
to add a feedback resistor externally to the chip though a
feedback resistor exists on-chip, insert a feedback
resistor between X
CIN
C
Rf
CIN
X
CIN
X
C
COUT
Rf
CIN
Rd
C
X
V
V
COUT
COUT
CC
IN
SS
Rd
C
and X
External oscillation
circuit
IN
COUT
and X
X
the input of the prescaler and
IN
CIN
OUT
X
IN
C
oscillations. The sufficient
following the instruction.
X
IN
Open
OUT
X
OUT
Rd (Note)
C
OUT
IN
) > 3 ×