M38507F8AFP#U1 Renesas Electronics America, M38507F8AFP#U1 Datasheet - Page 24

• Manufacturer Part Number: M38507F8AFP#U1
• Description: IC 740/3850 MCU FLASH 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38507F8AFP#U1

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 12.5 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: UART
• On-chip Adc: 9-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3850 Group (Spec.A QzROM version)
Rev.2.13
REJ03B0125-0213
TIMERS
The 3850 group (spec.A) has four timers: timer X, timer Y, timer
1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “00
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Fig 17. Structure of timer XY mode register
Fig 18. Structure of timer count source selection register
b7
b7
Apr 17, 2009
b0
b0
Timer count source selection register
(TCSS : address 0028
Timer X count source selection bit
0 : f(X
1 : f(X
Timer Y count source selection bit
0 : f(X
1 : f(X
Timer 12 count source selection bit
0 : f(X
1 : f(X
Not used (returns “0” when read)
Timer XY mode register
(TM : address 0023
Timer X operating mode bit
CNTR
Timer X count stop bit
Timer Y operating mode bits
CNTR
Timer Y count stop bit
b1 b0
b5 b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
0: Interrupt at falling edge
1: Interrupt at rising edge
0: Count start
1: Count stop
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
0: Interrupt at falling edge
1: Interrupt at rising edge
0: Count start
1: Count stop
Count at rising edge in event
counter mode
Count at falling edge in event
counter mode
Count at rising edge in event
counter mode
Count at falling edge in event
counter mode
IN
IN
IN
IN
IN
CIN
)/16 (f(X
)/2 (f(X
)/16 (f(X
)/2 (f(X
)/16 (f(X
0
1
)
Page 22 of 56
active edge selection bit
active edge selection bit
CIN
CIN
CIN
CIN
CIN
)/2 at low-speed mode)
)/2 at low-speed mode)
)/16 at low-speed mode)
)/16 at low-speed mode)
)/16 at low-speed mode)
16
16
)
)
16
”, an
• Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The
output of prescaler 12 is counted by timer 1 and timer 2, and a
timer underflow sets the interrupt request bit.
• Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count
source selection bit.
(2) Pulse Output Mode
The timer counts the count source selected by Timer count
source selection bit. Whenever the contents of the timer reach
“00
inverted. If the CNTR
“0”, output begins at “H”.
If it is “1”, output starts at “L”. When using a timer in this mode,
set the corresponding port P2
output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR
CNTR
When the CNTR
the rising edge of the CNTR
When the CNTR
the falling edge of the CNTR
(4) Pulse Width Measurement Mode
If the CNTR
timer counts the selected signals by the count source selection bit
while the CNTR
CNTR
the CNTR
The count can be stopped by setting “1” to the timer X (or timer
Y) count stop bit in any mode. The corresponding interrupt
request bit is set each time a timer underflows.
<Notes>
When switching the count source by the timer 12, X and Y count
source bits, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count input
signals.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
When timer X/timer Y underflow while executing the instruction
which sets “1” to the timer X/timer Y count stop bits, the timer
X/ timer Y interrupt request bits are set to “1”. Timer X/Timer Y
interrupts are received if these interrupts are enabled at this time.
The timing which interrupt is accepted has a case after the
instruction which sets “1” to the count stop bit, and a case after
the next instruction according to the timing of the timer
underflow. When this interrupt is unnecessary, set “0” (disabled)
to the interrupt enable bit and then set “1” to the count stop bit.
16
”, the signal output from the CNTR
1
1
) active edge selection bit is “1”, the timer counts it while
pin.
0
(or CNTR
0
(or CNTR
0
0
0
(or CNTR
(or CNTR
(or CNTR
1
0
) pin is at “L”.
(or CNTR
1
) active edge selection bit is “0”, the
0
0
1
7
1
1
(or CNTR
) pin is at “H”. If the CNTR
) active edge selection bit is “0”,
) active edge selection bit is “1”,
(or CNTR
(or port P4
1
) active edge selection bit is
1
1
) pin is counted.
) pin is counted.
0
) direction register to
0
(or CNTR
1
) pin is
0
0
(or
or