M3087BFKBGP#U3 Renesas Electronics America, M3087BFKBGP#U3 Datasheet - Page 332
M3087BFKBGP#U3
Manufacturer Part Number
M3087BFKBGP#U3
Description
IC M32C/87B MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFKBGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M3087BFKBGP#U3M3087BFKBGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 308 of 587
18.1.7
Table 18.10
Function
Analog input pins
Start condition
Stop condition
Interrupt request generation timing An interrupt request is generated every time each A/D conversion is completed
Reading A/D conversion result
In multi-port repeat sweep mode 0, analog voltage that is applied to 16 selected pins is repeatedly converted to
a digital code. Set the DUS bit in the AD0CON3 register to 1 (DMAC operating mode used).
Table 18.10 lists specifications of multi-port repeat sweep mode 0.
Multi-Port Repeat Sweep Mode 0
Item
Multi-Port Repeat Sweep Mode 0 Specifications
Analog voltage applied to the 16 selected pins is repeatedly converted in the
following order: AN_0 to AN_7 → ANi_0 to ANi_7 (i = 0, 2, 15)
Select one of the following.
• AN_0 → AN_1 →
• AN_0 → AN_1 →
• AN_0 → AN_1 →
The following register settings determine which pins are used:
Bits MPS11 and MPS10 in the AD0CON4 register
Software trigger is selected (TRG bit in the AD0CON0 register = 0):
• the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts)
External trigger, hardware trigger is selected (TRG bit = 1):
• TRG0 bit in the AD0CON2 register = 0
• TRG0 bit = 1
Set the ADST bit is set to 0 (A/D conversion stops)
(Set the DUS bit in the AD0CON3 register to 1)
A/D conversion result is stored into the AD00 register after A/D conversion is
completed. Then, DMAC transfers the data from the AD00 register to a given
memory space. Refer to 13. DMAC for DMAC settings (Set the DUS bit in the
AD0CON3 register to 1)
The falling edge is detected on the ADTRG pin after the ADST bit is set to 1
Timer B2 interrupt request of three-phase motor control timer function (after
the ICTB2 register completes counting) is generated after the ADST bit is set
to 1.
. . .
. . .
. . .
→ AN_7 → AN0_0 → AN0_1→
→ AN_7 → AN2_0 → AN2_1→
→ AN_7 → AN15_0 → AN15_1→
Specification
. . .
. . .
. . .
→ AN0_7
→ AN2_7
→ AN15_7
18. A/D Converter
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