M3087BFKBGP#U3 Renesas Electronics America, M3087BFKBGP#U3 Datasheet - Page 429
M3087BFKBGP#U3
Manufacturer Part Number
M3087BFKBGP#U3
Description
IC M32C/87B MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFKBGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M3087BFKBGP#U3M3087BFKBGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 405 of 587
23.1
Figure 23.3
23.1.1
Figures 23.3 to 23.19, 23.21 to 23.27, and 23.30 to 23.36 show the CAN-associated registers. Refer to 23.2 CAN
Clock and CPU Clock for details.
CANi Control Register 0 (i = 0, 1)
b15
NOTES:
1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock
2. Set both the RESET1 and RESET0 bits to the same value simultaneously.
CAN-Associated Registers
to the CAN module.
b8
CANi Control Register 0 (CiCTLR0 Register) (i = 0, 1)
b7
0
C0CTLR0 and C1CTLR0 Registers
b0
LOOPBACK
BASICCAN
Bit Symbol
TSRESET
ECRESET
(b15-b12)
RESET0
RESET1
TSPRE0
TSPRE1
(b7-b6)
(b2)
(b5)
Symbol
C0CTLR0
C1CTLR0
−
−
−
−
CAN reset bit 0
Loop back mode select bit
Unimplemented.
Write 0. Read as undefined value.
BasicCAN mode select bit
CAN reset bit 1
Reserved bit
Unimplemented.
Write 0. Read as undefined value.
Time stamp prescaler
select bits
Time stamp counter reset bit
Error counter reset bit
Unimplemented.
Write 0. Read as undefined value.
Bit Name
(2)
(2)
Address
0201h - 0200h
0281h - 0280h
0: CAN module is out of reset
1: CAN module is reset
0: Loop back function disabled
1: Loop back function enabled
0: BasicCAN mode function disabled
1: BasicCAN mode function enabled
0: CAN module is out of reset
1: CAN module is reset
Set to 0
b9 b8
0 0: CAN bus bit clock
0 1: CAN bus bit clock divided by 2 selected
1 0: CAN bus bit clock divided by 3 selected
1 1: CAN bus bit clock divided by 4 selected
0: Nothing occurs
1: The CiTSR register becomes 0000h, then this
0: Nothing occurs
1: Registers CiTEC and CiREC become 00h,
bit is automatically set back to 0
then this bit is automatically set back to 0
Function
After Reset
XXXX 0000 XX01 0X01b
XXXX 0000 XX01 0X01b
(1)
23. CAN Module
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
−
−
−
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