M3087BFKBGP#U3 Renesas Electronics America, M3087BFKBGP#U3 Datasheet - Page 601
M3087BFKBGP#U3
Manufacturer Part Number
M3087BFKBGP#U3
Description
IC M32C/87B MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFKBGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M3087BFKBGP#U3M3087BFKBGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 577 of 587
28.14 CAN
Figure 28.6
Figure 28.7
Use the following procedures to abort a remote frame transmit operation or to cancel a remote frame receive
operation. (Technical update: TN-16C-126A/EA)
i = 0, 1, j = 0 to 15
NOTES:
i = 0, 1, j = 0 to 15
NOTES:
1. The CiMCTLj register can be accessed when the BANKSEL bit the CiCTLR1 register is set to 0
2. There is an infinite loop set in the flowchart to simplify the description. Set the time limit to break
1. The CiMCTLj register can be accessed when the BANKSEL bit the CiCTLR1 register is set to 0
2. There is an infinite loop set in the flowchart to simplify the description. Set the time limit to break
(note 2)
Procedure to Abort a Remote Frame Transmit Operation
Procedure to Cancel a Remote Frame Receive Operation
(note 2)
(registers CiMCTLj, CiSSCTLR, and CiSSSTR are selected).
out of the infinite loop for practical use.
(registers CiMCTLj, CiSSCTLR, and CiSSSTR are selected).
out of each infinite loop for practical use.
NO
NO
CiMCTLj register: REMACTIVE bit is 0 ?
CiMCTLj register: REMACTIVE bit = 0 ?
Read the CiMCTLj register
Read the CiMCTLj register
Start of transmit operation
End of transmit operation
Start of receive operation
End of receive operation
CiMCTLj register = 00h
CiMCTLj register = 00h
cancel procedure
cancel procedure
abort procedure
abort procedure
YES
YES
(note 1)
(note 1)
28. Usage Notes
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